riscv/rocket-chip
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Merge branch 'master' of github.com:ucb-bar/reference-chip

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This commit is contained in:
Ben Keller 2013-07-10 16:01:25 -07:00
commit c7bf1aaac9
5 changed files with 5 additions and 5 deletions
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2
chisel

@ -1 +1 @@
Subproject commit 11cb15ba9a0f7dedf43a34e0d64708facd0ea619
Subproject commit 2c93b2d07d54e4eaeb7aec347a3fc9f0fec5a48d

2
riscv-rocket

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Subproject commit 00a230c369fa8d04fd702e2fc7f2394cdcba55a9
Subproject commit 9ace637d7b28e2aff7289fea094f5d8d8eb83212

2
src/main/scala/RocketChip.scala
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@ -298,7 +298,7 @@ class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAge
val conv = new MemIOUncachedTileLinkIOConverter(2)(ucWithHtifConf)
if(lnWithHtifConf.nMasters > 1) {
val arb = new UncachedTileLinkIOArbiter(lnWithHtifConf.nMasters, conf.co)(lnWithHtifConf)
val arb = new UncachedTileLinkIOArbiterThatAppendsArbiterId(lnWithHtifConf.nMasters, conf.co)(lnWithHtifConf)
arb.io.in zip masterEndpoints.map(_.io.master) map { case (arb, cache) => arb <> cache }
conv.io.uncached <> arb.io.out
} else {

2
src/main/scala/fpga.scala
View File

@ -31,7 +31,7 @@ class FPGAOuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenc
val conv = new MemIOUncachedTileLinkIOConverter(2)(ucWithHtifConf)
if(lnWithHtifConf.nMasters > 1) {
val arb = new UncachedTileLinkIOArbiter(lnWithHtifConf.nMasters, conf.co)(lnWithHtifConf)
val arb = new UncachedTileLinkIOArbiterThatAppendsArbiterId(lnWithHtifConf.nMasters, conf.co)(lnWithHtifConf)
arb.io.in zip masterEndpoints.map(_.io.master) map { case (arb, cache) => arb <> cache }
conv.io.uncached <> arb.io.out
} else {

2
uncore

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Subproject commit f238f04fd9cd9751a515a129e474d4ffc8631817
Subproject commit cd75291f2969e46fc6cf62c9519e675c27c06eb4