From 2796de01bfc3ac5cd653623904b5faed51ee6c46 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 9 Jul 2013 15:41:27 -0700 Subject: [PATCH] new tilelink arbiter types, reduced release xact trackers --- chisel | 2 +- riscv-rocket | 2 +- riscv-tools | 2 +- src/main/scala/RocketChip.scala | 2 +- src/main/scala/fpga.scala | 2 +- uncore | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/chisel b/chisel index 11cb15ba..2c93b2d0 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit 11cb15ba9a0f7dedf43a34e0d64708facd0ea619 +Subproject commit 2c93b2d07d54e4eaeb7aec347a3fc9f0fec5a48d diff --git a/riscv-rocket b/riscv-rocket index 00a230c3..9ace637d 160000 --- a/riscv-rocket +++ b/riscv-rocket @@ -1 +1 @@ -Subproject commit 00a230c369fa8d04fd702e2fc7f2394cdcba55a9 +Subproject commit 9ace637d7b28e2aff7289fea094f5d8d8eb83212 diff --git a/riscv-tools b/riscv-tools index e3c80a86..e35c6e97 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit e3c80a865af83a022a796284e02040b0539b835a +Subproject commit e35c6e9735eebc26edbc626e83bb27cb520134b6 diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 91137d9e..5a913957 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -298,7 +298,7 @@ class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAge val conv = new MemIOUncachedTileLinkIOConverter(2)(ucWithHtifConf) if(lnWithHtifConf.nMasters > 1) { - val arb = new UncachedTileLinkIOArbiter(lnWithHtifConf.nMasters, conf.co)(lnWithHtifConf) + val arb = new UncachedTileLinkIOArbiterThatAppendsArbiterId(lnWithHtifConf.nMasters, conf.co)(lnWithHtifConf) arb.io.in zip masterEndpoints.map(_.io.master) map { case (arb, cache) => arb <> cache } conv.io.uncached <> arb.io.out } else { diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala index d690e85e..e71483c5 100644 --- a/src/main/scala/fpga.scala +++ b/src/main/scala/fpga.scala @@ -31,7 +31,7 @@ class FPGAOuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenc val conv = new MemIOUncachedTileLinkIOConverter(2)(ucWithHtifConf) if(lnWithHtifConf.nMasters > 1) { - val arb = new UncachedTileLinkIOArbiter(lnWithHtifConf.nMasters, conf.co)(lnWithHtifConf) + val arb = new UncachedTileLinkIOArbiterThatAppendsArbiterId(lnWithHtifConf.nMasters, conf.co)(lnWithHtifConf) arb.io.in zip masterEndpoints.map(_.io.master) map { case (arb, cache) => arb <> cache } conv.io.uncached <> arb.io.out } else { diff --git a/uncore b/uncore index f238f04f..cd75291f 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit f238f04fd9cd9751a515a129e474d4ffc8631817 +Subproject commit cd75291f2969e46fc6cf62c9519e675c27c06eb4