riscv/rocket-chip
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Merge branch 'master' of github.com:ucb-bar/reference-chip

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This commit is contained in:
Ben Keller
2013-07-10 16:01:25 -07:00
parent a72e0dc99e 2796de01bf
commit c7bf1aaac9
5 changed files with 5 additions and 5 deletions
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2
chisel

Submodule chisel updated: 11cb15ba9a...2c93b2d07d

2
riscv-rocket

Submodule riscv-rocket updated: 00a230c369...9ace637d7b

2
src/main/scala/RocketChip.scala
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@ -298,7 +298,7 @@ class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAge
val conv = new MemIOUncachedTileLinkIOConverter(2)(ucWithHtifConf) val conv = new MemIOUncachedTileLinkIOConverter(2)(ucWithHtifConf)
if(lnWithHtifConf.nMasters > 1) { if(lnWithHtifConf.nMasters > 1) {
val arb = new UncachedTileLinkIOArbiter(lnWithHtifConf.nMasters, conf.co)(lnWithHtifConf) val arb = new UncachedTileLinkIOArbiterThatAppendsArbiterId(lnWithHtifConf.nMasters, conf.co)(lnWithHtifConf)
arb.io.in zip masterEndpoints.map(_.io.master) map { case (arb, cache) => arb <> cache } arb.io.in zip masterEndpoints.map(_.io.master) map { case (arb, cache) => arb <> cache }
conv.io.uncached <> arb.io.out conv.io.uncached <> arb.io.out
} else { } else {

2
src/main/scala/fpga.scala
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@ -31,7 +31,7 @@ class FPGAOuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenc
val conv = new MemIOUncachedTileLinkIOConverter(2)(ucWithHtifConf) val conv = new MemIOUncachedTileLinkIOConverter(2)(ucWithHtifConf)
if(lnWithHtifConf.nMasters > 1) { if(lnWithHtifConf.nMasters > 1) {
val arb = new UncachedTileLinkIOArbiter(lnWithHtifConf.nMasters, conf.co)(lnWithHtifConf) val arb = new UncachedTileLinkIOArbiterThatAppendsArbiterId(lnWithHtifConf.nMasters, conf.co)(lnWithHtifConf)
arb.io.in zip masterEndpoints.map(_.io.master) map { case (arb, cache) => arb <> cache } arb.io.in zip masterEndpoints.map(_.io.master) map { case (arb, cache) => arb <> cache }
conv.io.uncached <> arb.io.out conv.io.uncached <> arb.io.out
} else { } else {

2
uncore

Submodule uncore updated: f238f04fd9...cd75291f29