Merge branch 'master' of github.com:ucb-bar/reference-chip
This commit is contained in:
commit
c7bf1aaac9
2
chisel
2
chisel
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Subproject commit 11cb15ba9a0f7dedf43a34e0d64708facd0ea619
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Subproject commit 2c93b2d07d54e4eaeb7aec347a3fc9f0fec5a48d
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Subproject commit 00a230c369fa8d04fd702e2fc7f2394cdcba55a9
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Subproject commit 9ace637d7b28e2aff7289fea094f5d8d8eb83212
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@ -298,7 +298,7 @@ class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAge
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val conv = new MemIOUncachedTileLinkIOConverter(2)(ucWithHtifConf)
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val conv = new MemIOUncachedTileLinkIOConverter(2)(ucWithHtifConf)
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if(lnWithHtifConf.nMasters > 1) {
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if(lnWithHtifConf.nMasters > 1) {
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val arb = new UncachedTileLinkIOArbiter(lnWithHtifConf.nMasters, conf.co)(lnWithHtifConf)
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val arb = new UncachedTileLinkIOArbiterThatAppendsArbiterId(lnWithHtifConf.nMasters, conf.co)(lnWithHtifConf)
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arb.io.in zip masterEndpoints.map(_.io.master) map { case (arb, cache) => arb <> cache }
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arb.io.in zip masterEndpoints.map(_.io.master) map { case (arb, cache) => arb <> cache }
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conv.io.uncached <> arb.io.out
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conv.io.uncached <> arb.io.out
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} else {
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} else {
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@ -31,7 +31,7 @@ class FPGAOuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenc
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val conv = new MemIOUncachedTileLinkIOConverter(2)(ucWithHtifConf)
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val conv = new MemIOUncachedTileLinkIOConverter(2)(ucWithHtifConf)
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if(lnWithHtifConf.nMasters > 1) {
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if(lnWithHtifConf.nMasters > 1) {
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val arb = new UncachedTileLinkIOArbiter(lnWithHtifConf.nMasters, conf.co)(lnWithHtifConf)
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val arb = new UncachedTileLinkIOArbiterThatAppendsArbiterId(lnWithHtifConf.nMasters, conf.co)(lnWithHtifConf)
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arb.io.in zip masterEndpoints.map(_.io.master) map { case (arb, cache) => arb <> cache }
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arb.io.in zip masterEndpoints.map(_.io.master) map { case (arb, cache) => arb <> cache }
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conv.io.uncached <> arb.io.out
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conv.io.uncached <> arb.io.out
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} else {
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} else {
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2
uncore
2
uncore
@ -1 +1 @@
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Subproject commit f238f04fd9cd9751a515a129e474d4ffc8631817
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Subproject commit cd75291f2969e46fc6cf62c9519e675c27c06eb4
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