diff --git a/riscv-tools b/riscv-tools
index 40a956a7..b8fe37d1 160000
--- a/riscv-tools
+++ b/riscv-tools
@@ -1 +1 @@
-Subproject commit 40a956a7a5335c051416a69eed7d28936b8d967a
+Subproject commit b8fe37d17fe4c5be14af6f4975056cdce81691d7
diff --git a/rocket b/rocket
index 8869c1a4..2b5831d9 160000
--- a/rocket
+++ b/rocket
@@ -1 +1 @@
-Subproject commit 8869c1a44aa91c303eb5ea2bf880e4d74806fce7
+Subproject commit 2b5831d9226258f15d28d16135da464f30aac603
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 72bf90c8..b4b714b8 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -218,6 +218,10 @@ class Uncore(implicit val p: Parameters) extends Module
     val bootROMAddr = ioAddrHashMap("int:bootrom")
     bootROM.io <> mmioNetwork.io.out(bootROMAddr.port)
 
+    val debugModule = Module(new ROMSlave(Seq())) // TODO
+    val debugModuleAddr = ioAddrHashMap("int:debug")
+    debugModule.io <> mmioNetwork.io.out(debugModuleAddr.port)
+
     TopUtils.connectTilelinkNasti(io.mmio, mmioNetwork.io.out(ioAddrHashMap("ext").port))
   }
 }