riscv/rocket-chip
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make sure TL parameters change properly throughout

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* Outermost TL parameters should have the width set to be the same as the
   MIF data width.
 * Broadcast Hub and Narrower, which use different sets of TL parameters
   should use the proper set of parameters at each interface
This commit is contained in:
Howard Mao
2015-10-14 17:59:49 -07:00
parent 4270fd78a5
commit c4117eb9a2
2 changed files with 13 additions and 2 deletions
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13
src/main/scala/Configs.scala
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@@ -151,7 +151,18 @@ class DefaultConfig extends ChiselConfig (
maxManagerXacts = 1, maxManagerXacts = 1,
addrBits = site(PAddrBits) - site(CacheBlockOffsetBits), addrBits = site(PAddrBits) - site(CacheBlockOffsetBits),
dataBits = site(CacheBlockBytes)*8)() dataBits = site(CacheBlockBytes)*8)()
case TLKey("Outermost") => site(TLKey("L2toMC")) case TLKey("Outermost") =>
TileLinkParameters(
coherencePolicy = new MEICoherence(new NullRepresentation(site(NBanksPerMemoryChannel))),
nManagers = 1,
nCachingClients = site(NBanksPerMemoryChannel),
nCachelessClients = 0,
maxClientXacts = 1,
maxClientsPerPort = site(NAcquireTransactors) + 2,
maxManagerXacts = 1,
addrBits = site(PAddrBits) - site(CacheBlockOffsetBits),
dataBits = site(CacheBlockBytes)*8,
dataBeats = site(MIFDataBeats))()
case NTiles => Knob("NTILES") case NTiles => Knob("NTILES")
case NMemoryChannels => 1 case NMemoryChannels => 1
case NBanksPerMemoryChannel => Knob("NBANKS") case NBanksPerMemoryChannel => Knob("NBANKS")

2
uncore

Submodule uncore updated: b0eece1f61...aa40f7d7c1