From c4117eb9a23d2cb7c3291f276f7e1d6bfdfe38f3 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Wed, 14 Oct 2015 17:59:49 -0700
Subject: [PATCH] make sure TL parameters change properly throughout

 * Outermost TL parameters should have the width set to be the same as the
   MIF data width.
 * Broadcast Hub and Narrower, which use different sets of TL parameters
   should use the proper set of parameters at each interface
---
 src/main/scala/Configs.scala | 13 ++++++++++++-
 uncore                       |  2 +-
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index c0741726..d7ed791d 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -151,7 +151,18 @@ class DefaultConfig extends ChiselConfig (
           maxManagerXacts = 1,
           addrBits = site(PAddrBits) - site(CacheBlockOffsetBits),
           dataBits = site(CacheBlockBytes)*8)()
-      case TLKey("Outermost") => site(TLKey("L2toMC"))
+      case TLKey("Outermost") =>
+        TileLinkParameters(
+          coherencePolicy = new MEICoherence(new NullRepresentation(site(NBanksPerMemoryChannel))),
+          nManagers = 1,
+          nCachingClients = site(NBanksPerMemoryChannel),
+          nCachelessClients = 0,
+          maxClientXacts = 1,
+          maxClientsPerPort = site(NAcquireTransactors) + 2,
+          maxManagerXacts = 1,
+          addrBits = site(PAddrBits) - site(CacheBlockOffsetBits),
+          dataBits = site(CacheBlockBytes)*8,
+          dataBeats = site(MIFDataBeats))()
       case NTiles => Knob("NTILES")
       case NMemoryChannels => 1
       case NBanksPerMemoryChannel => Knob("NBANKS")
diff --git a/uncore b/uncore
index b0eece1f..aa40f7d7 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit b0eece1f613d4aafa3f9cf5470576ffb5110e856
+Subproject commit aa40f7d7c11b5dd099376baf73b998da859a1616