riscv/rocket-chip
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rocketchip: remove pbus; TL2 has swallowed it completely

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This commit is contained in:
Wesley W. Terpstra
2016-10-25 18:18:06 -07:00
parent 10d084b9f3
commit c3dacca39a
5 changed files with 7 additions and 12 deletions
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6
src/main/scala/rocketchip/BaseTop.scala
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@@ -80,11 +80,7 @@ abstract class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle[L]](
val coreplex = p(BuildCoreplex)(outer.c, p)
val coreplexIO = Wire(coreplex.io)
val pBus =
Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).subMap("io:pbus"))(
p.alterPartial({ case TLId => "L2toMMIO" })))
pBus.io.in.head <> coreplexIO.master.mmio
outer.legacy.module.io.legacy <> pBus.port("TL2")
outer.legacy.module.io.legacy <> coreplexIO.master.mmio
println("Generated Address Map")
for (entry <- p(GlobalAddrMap).flatten) {