From c3dacca39a7ae45239226fc883c12c59de4638d9 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Tue, 25 Oct 2016 18:18:06 -0700
Subject: [PATCH] rocketchip: remove pbus; TL2 has swallowed it completely

---
 src/main/scala/coreplex/BaseCoreplex.scala | 2 +-
 src/main/scala/groundtest/Configs.scala    | 2 +-
 src/main/scala/groundtest/Regression.scala | 2 +-
 src/main/scala/rocketchip/BaseTop.scala    | 6 +-----
 src/main/scala/rocketchip/Utils.scala      | 7 +++----
 5 files changed, 7 insertions(+), 12 deletions(-)

diff --git a/src/main/scala/coreplex/BaseCoreplex.scala b/src/main/scala/coreplex/BaseCoreplex.scala
index 63da5222..3210ec36 100644
--- a/src/main/scala/coreplex/BaseCoreplex.scala
+++ b/src/main/scala/coreplex/BaseCoreplex.scala
@@ -167,7 +167,7 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
     for ((t, m) <- (uncoreTileIOs.map(_.slave).flatten) zip (tileSlavePorts map (cBus port _)))
       t <> m
 
-    io.master.mmio <> cBus.port("pbus")
+    io.master.mmio <> cBus.port("TL2")
   }
 
   // Coreplex doesn't know when to stop running
diff --git a/src/main/scala/groundtest/Configs.scala b/src/main/scala/groundtest/Configs.scala
index 7f5bc0eb..61dee763 100644
--- a/src/main/scala/groundtest/Configs.scala
+++ b/src/main/scala/groundtest/Configs.scala
@@ -121,7 +121,7 @@ class WithComparator extends Config(
     case BuildGroundTest =>
       (p: Parameters) => Module(new ComparatorCore()(p))
     case ComparatorKey => ComparatorParameters(
-      targets    = Seq("mem", "io:pbus:TL2:testram").map(name =>
+      targets    = Seq("mem", "io:TL2:testram").map(name =>
                     site(GlobalAddrMap)(name).start.longValue),
       width      = 8,
       operations = 1000,
diff --git a/src/main/scala/groundtest/Regression.scala b/src/main/scala/groundtest/Regression.scala
index cf0fefe7..093855fe 100644
--- a/src/main/scala/groundtest/Regression.scala
+++ b/src/main/scala/groundtest/Regression.scala
@@ -71,7 +71,7 @@ class IOGetAfterPutBlockRegression(implicit p: Parameters) extends Regression()(
   io.mem.grant.ready := Bool(true)
 
   io.cache.req.valid := !get_sent && started
-  io.cache.req.bits.addr := UInt(addrMap("io:pbus:TL2:bootrom").start)
+  io.cache.req.bits.addr := UInt(addrMap("io:TL2:bootrom").start)
   io.cache.req.bits.typ := MT_WU
   io.cache.req.bits.cmd := M_XRD
   io.cache.req.bits.tag := UInt(0)
diff --git a/src/main/scala/rocketchip/BaseTop.scala b/src/main/scala/rocketchip/BaseTop.scala
index 3cec7521..82f3b824 100644
--- a/src/main/scala/rocketchip/BaseTop.scala
+++ b/src/main/scala/rocketchip/BaseTop.scala
@@ -80,11 +80,7 @@ abstract class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle[L]](
   val coreplex = p(BuildCoreplex)(outer.c, p)
   val coreplexIO = Wire(coreplex.io)
 
-  val pBus =
-    Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).subMap("io:pbus"))(
-      p.alterPartial({ case TLId => "L2toMMIO" })))
-  pBus.io.in.head <> coreplexIO.master.mmio
-  outer.legacy.module.io.legacy <> pBus.port("TL2")
+  outer.legacy.module.io.legacy <> coreplexIO.master.mmio
 
   println("Generated Address Map")
   for (entry <- p(GlobalAddrMap).flatten) {
diff --git a/src/main/scala/rocketchip/Utils.scala b/src/main/scala/rocketchip/Utils.scala
index 7558297b..c04b23e0 100644
--- a/src/main/scala/rocketchip/Utils.scala
+++ b/src/main/scala/rocketchip/Utils.scala
@@ -90,15 +90,14 @@ object GenerateGlobalAddrMap {
       }).flatten.toList
 
     lazy val tl2AddrMap = new AddrMap(uniquelyNamedTL2Devices, collapse = true)
-    lazy val pBusIOAddrMap = new AddrMap(Seq(AddrMapEntry("TL2", tl2AddrMap)), collapse = true)
 
     val memBase = 0x80000000L
     val memSize = p(ExtMemSize)
     Dump("MEM_BASE", memBase)
 
     val cBus = AddrMapEntry("cbus", cBusIOAddrMap)
-    val pBus = AddrMapEntry("pbus", pBusIOAddrMap)
-    val io = AddrMapEntry("io", AddrMap((cBus +: (!pBusIOAddrMap.isEmpty).option(pBus).toSeq):_*))
+    val tlBus = AddrMapEntry("TL2", tl2AddrMap)
+    val io = AddrMapEntry("io", AddrMap(cBus, tlBus))
     val mem = AddrMapEntry("mem", MemRange(memBase, memSize, MemAttr(AddrMapProt.RWX, true)))
     AddrMap((io +: (p(NMemoryChannels) > 0).option(mem).toSeq):_*)
   }
@@ -108,7 +107,7 @@ object GenerateConfigString {
   def apply(p: Parameters, c: CoreplexConfig, peripheryManagers: Seq[TLManagerParameters]) = {
     val addrMap = p(GlobalAddrMap)
     val plicAddr = addrMap("io:cbus:plic").start
-    val clint = CoreplexLocalInterrupterConfig(0, addrMap("io:pbus:TL2:clint").start)
+    val clint = CoreplexLocalInterrupterConfig(0, addrMap("io:TL2:clint").start)
     val xLen = p(XLen)
     val res = new StringBuilder
     res append  "plic {\n"