rocketchip: remove pbus; TL2 has swallowed it completely

2016-10-25 18:18:06 -07:00
parent 10d084b9f3
commit c3dacca39a
5 changed files with 7 additions and 12 deletions
--- a/src/main/scala/coreplex/BaseCoreplex.scala
+++ b/src/main/scala/coreplex/BaseCoreplex.scala
@ -167,7 +167,7 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
    for ((t, m) <- (uncoreTileIOs.map(_.slave).flatten) zip (tileSlavePorts map (cBus port _)))
      t <> m

-    io.master.mmio <> cBus.port("pbus")
+    io.master.mmio <> cBus.port("TL2")
  }

  // Coreplex doesn't know when to stop running