riscv/rocket-chip
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clean up priority encoders

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This commit is contained in:
Andrew Waterman
2012-02-29 16:13:14 -08:00
parent b9ec69f8f5
commit c38065d0e8
4 changed files with 16 additions and 58 deletions
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6
rocket/src/main/scala/nbdcache.scala
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@ -361,10 +361,8 @@ class ReplayUnit extends Component {
val cpu_resp_tag = Bits(DCACHE_TAG_BITS, OUTPUT)
}
val sdq_val = Reg(resetVal = UFix(0, NSDQ))
val sdq_allocator = new priorityEncoder(NSDQ)
sdq_allocator.io.in := ~sdq_val
val sdq_alloc_id = sdq_allocator.io.out.toUFix
val sdq_val = Reg(resetVal = UFix(0))
val sdq_alloc_id = PriorityEncoder(~sdq_val(NSDQ-1,0))
val replay_val = Reg(resetVal = Bool(false))
val replay_retry = replay_val && !io.data_req.ready