From c38065d0e879644c6b519c52a17239742e59a410 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 29 Feb 2012 16:13:14 -0800 Subject: [PATCH] clean up priority encoders --- rocket/src/main/scala/dtlb.scala | 11 +++---- rocket/src/main/scala/itlb.scala | 11 +++---- rocket/src/main/scala/nbdcache.scala | 6 ++-- rocket/src/main/scala/util.scala | 46 ++++------------------------ 4 files changed, 16 insertions(+), 58 deletions(-) diff --git a/rocket/src/main/scala/dtlb.scala b/rocket/src/main/scala/dtlb.scala index 6c0af2a0..eb7a91cf 100644 --- a/rocket/src/main/scala/dtlb.scala +++ b/rocket/src/main/scala/dtlb.scala @@ -118,12 +118,9 @@ class rocketDTLB(entries: Int) extends Component } // high if there are any unused (invalid) entries in the TLB - val invalid_entry = (tag_cam.io.valid_bits != ~Bits(0,entries)); - val ie_enc = new priorityEncoder(entries); - ie_enc.io.in := ~tag_cam.io.valid_bits.toUFix; - val ie_addr = ie_enc.io.out; - - val repl_waddr = Mux(invalid_entry, ie_addr, repl_count).toUFix; + val has_invalid_entry = !tag_cam.io.valid_bits.andR + val invalid_entry = PriorityEncoder(~tag_cam.io.valid_bits) + val repl_waddr = Mux(has_invalid_entry, invalid_entry, repl_count).toUFix; val lookup = (state === s_ready) && r_cpu_req_val && !io.cpu_req.bits.kill && (req_load || req_store || req_amo || req_pf); val lookup_hit = lookup && tag_hit; @@ -136,7 +133,7 @@ class rocketDTLB(entries: Int) extends Component when (tlb_miss) { r_refill_tag := lookup_tag; r_refill_waddr := repl_waddr; - when (!invalid_entry) { + when (!has_invalid_entry) { repl_count := repl_count + UFix(1); } } diff --git a/rocket/src/main/scala/itlb.scala b/rocket/src/main/scala/itlb.scala index 231010b9..06cd6e2b 100644 --- a/rocket/src/main/scala/itlb.scala +++ b/rocket/src/main/scala/itlb.scala @@ -146,12 +146,9 @@ class rocketITLB(entries: Int) extends Component } // high if there are any unused entries in the ITLB - val invalid_entry = (tag_cam.io.valid_bits != ~Bits(0,entries)); - val ie_enc = new priorityEncoder(entries); - ie_enc.io.in := ~tag_cam.io.valid_bits.toUFix; - val ie_addr = ie_enc.io.out; - - val repl_waddr = Mux(invalid_entry, ie_addr, repl_count).toUFix; + val has_invalid_entry = !tag_cam.io.valid_bits.andR + val invalid_entry = PriorityEncoder(~tag_cam.io.valid_bits) + val repl_waddr = Mux(has_invalid_entry, invalid_entry, repl_count).toUFix; val lookup = (state === s_ready) && r_cpu_req_val; val lookup_hit = lookup && tag_hit; @@ -162,7 +159,7 @@ class rocketITLB(entries: Int) extends Component when (tlb_miss) { r_refill_tag := lookup_tag; r_refill_waddr := repl_waddr; - when (!invalid_entry) { + when (!has_invalid_entry) { repl_count := repl_count + UFix(1); } } diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index 50dd9fc3..57d223b6 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -361,10 +361,8 @@ class ReplayUnit extends Component { val cpu_resp_tag = Bits(DCACHE_TAG_BITS, OUTPUT) } - val sdq_val = Reg(resetVal = UFix(0, NSDQ)) - val sdq_allocator = new priorityEncoder(NSDQ) - sdq_allocator.io.in := ~sdq_val - val sdq_alloc_id = sdq_allocator.io.out.toUFix + val sdq_val = Reg(resetVal = UFix(0)) + val sdq_alloc_id = PriorityEncoder(~sdq_val(NSDQ-1,0)) val replay_val = Reg(resetVal = Bool(false)) val replay_retry = replay_val && !io.data_req.ready diff --git a/rocket/src/main/scala/util.scala b/rocket/src/main/scala/util.scala index 47361d2e..23209a4f 100644 --- a/rocket/src/main/scala/util.scala +++ b/rocket/src/main/scala/util.scala @@ -211,46 +211,12 @@ class Arbiter[T <: Data](n: Int)(data: => T) extends Component { dout <> io.out.bits } -class ioPriorityDecoder(in_width: Int, out_width: Int) extends Bundle +object PriorityEncoder { - val in = UFix(in_width, INPUT); - val out = Bits(out_width, OUTPUT); -} - -class priorityDecoder(width: Int) extends Component -{ - val in_width = ceil(log10(width)/log10(2)).toInt; - val io = new ioPriorityEncoder(in_width, width); - val l_out = Wire() { Bits() }; - - l_out := Bits(0, width); - for (i <- width-1 to 0 by -1) { - when (io.in === UFix(i, in_width)) { - l_out := Bits(1,1) << UFix(i); - } + def apply(in: Bits, n: Int = 0): UFix = { + if (n >= in.getWidth-1) + UFix(n) + else + Mux(in(n), UFix(n), PriorityEncoder(in, n+1)) } - - io.out := l_out; -} - -class ioPriorityEncoder(in_width: Int, out_width: Int) extends Bundle -{ - val in = Bits(in_width, INPUT); - val out = UFix(out_width, OUTPUT); -} - -class priorityEncoder(width: Int) extends Component -{ - val out_width = ceil(log10(width)/log10(2)).toInt; - val io = new ioPriorityDecoder(width, out_width); - val l_out = Wire() { UFix() }; - - l_out := UFix(0, out_width); - for (i <- width-1 to 1 by -1) { - when (io.in(i).toBool) { - l_out := UFix(i, out_width); - } - } - - io.out := l_out; }