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ResetCatchAndSync: work also in the context of a RawModule (#1202)

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This commit is contained in:
Wesley W. Terpstra
2018-01-19 19:45:52 -08:00
committed by GitHub
parent f6f5606f8e
commit c32150b994
1 changed files with 7 additions and 6 deletions
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13
src/main/scala/util/ResetCatchAndSync.scala
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@@ -3,6 +3,7 @@
package freechips.rocketchip.util
import Chisel._
import chisel3.experimental.{withClockAndReset}
/** Reset: asynchronous assert,
* synchronous de-assert
@@ -28,12 +29,12 @@ object ResetCatchAndSync {
def apply(clk: Clock, rst: Bool, sync: Int = 3, name: Option[String] = None,
psd: Option[PSDTestMode] = None): Bool = {
val catcher = Module (new ResetCatchAndSync(sync))
if (name.isDefined) {catcher.suggestName(name.get)}
catcher.clock := clk
catcher.reset := rst
catcher.io.psd <> psd.getOrElse(Wire(new PSDTestMode()).fromBits(UInt(0)))
catcher.io.sync_reset
withClockAndReset(clk, rst) {
val catcher = Module (new ResetCatchAndSync(sync))
if (name.isDefined) {catcher.suggestName(name.get)}
catcher.io.psd <> psd.getOrElse(Wire(new PSDTestMode()).fromBits(UInt(0)))
catcher.io.sync_reset
}
}
def apply(clk: Clock, rst: Bool, sync: Int, name: String): Bool = apply(clk, rst, sync, Some(name))