From c32150b9948761f7759395948084a6d68a9aa016 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 19 Jan 2018 19:45:52 -0800 Subject: [PATCH] ResetCatchAndSync: work also in the context of a RawModule (#1202) --- src/main/scala/util/ResetCatchAndSync.scala | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/src/main/scala/util/ResetCatchAndSync.scala b/src/main/scala/util/ResetCatchAndSync.scala index 343ca939..a83e3300 100644 --- a/src/main/scala/util/ResetCatchAndSync.scala +++ b/src/main/scala/util/ResetCatchAndSync.scala @@ -3,6 +3,7 @@ package freechips.rocketchip.util import Chisel._ +import chisel3.experimental.{withClockAndReset} /** Reset: asynchronous assert, * synchronous de-assert @@ -28,12 +29,12 @@ object ResetCatchAndSync { def apply(clk: Clock, rst: Bool, sync: Int = 3, name: Option[String] = None, psd: Option[PSDTestMode] = None): Bool = { - val catcher = Module (new ResetCatchAndSync(sync)) - if (name.isDefined) {catcher.suggestName(name.get)} - catcher.clock := clk - catcher.reset := rst - catcher.io.psd <> psd.getOrElse(Wire(new PSDTestMode()).fromBits(UInt(0))) - catcher.io.sync_reset + withClockAndReset(clk, rst) { + val catcher = Module (new ResetCatchAndSync(sync)) + if (name.isDefined) {catcher.suggestName(name.get)} + catcher.io.psd <> psd.getOrElse(Wire(new PSDTestMode()).fromBits(UInt(0))) + catcher.io.sync_reset + } } def apply(clk: Clock, rst: Bool, sync: Int, name: String): Bool = apply(clk, rst, sync, Some(name))