Merge pull request #796 from freechipsproject/buffer-instance

diplomacy: BufferParams can now directly create a Queue

src/main/scala/coreplex/CoreplexNetwork.scala

@@ -173,7 +173,7 @@ trait BankedL2CoherenceManagers extends CoreplexNetwork {
     val node = TLOutputNode()
     for (bank <- 0 until l2Config.nBanksPerChannel) {
       val offset = (bank * l2Config.nMemoryChannels) + channel
-      in := TLBuffer(BufferParams.flow, BufferParams.none)(l1tol2.node)
+      in := l1tol2.node
       node := TLFilter(AddressSet(offset * l1tol2_lineBytes, mask))(out)
     }
     node

src/main/scala/diplomacy/Parameters.scala

@@ -248,6 +248,10 @@ case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
   require (depth >= 0, "Buffer depth must be >= 0")
   def isDefined = depth > 0
   def latency = if (isDefined && !flow) 1 else 0
+
+  def apply[T <: Data](x: DecoupledIO[T]) =
+    if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
+    else x
 }
 
 object BufferParams

src/main/scala/uncore/tilelink2/Buffer.scala

@@ -29,22 +29,14 @@ class TLBuffer(
       val out = node.bundleOut
     }
 
-    def buffer[T <: Data](config: BufferParams, data: DecoupledIO[T]): DecoupledIO[T] = {
-      if (config.isDefined) {
-        Queue(data, config.depth, pipe=config.pipe, flow=config.flow)
-      } else {
-        data
-      }
-    }
-
     ((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
-      out.a <> buffer(a, in .a)
-      in .d <> buffer(d, out.d)
+      out.a <> a(in .a)
+      in .d <> d(out.d)
 
       if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
-        in .b <> buffer(b, out.b)
-        out.c <> buffer(c, in .c)
-        out.e <> buffer(e, in .e)
+        in .b <> b(out.b)
+        out.c <> c(in .c)
+        out.e <> e(in .e)
       } else {
         in.b.valid := Bool(false)
         in.c.ready := Bool(true)