From 4a15d47061415ad28d6f132ebc464ef9c8373fc5 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Wed, 14 Jun 2017 13:45:12 -0700
Subject: [PATCH 1/2] diplomacy: BufferParams can now directly create a Queue

---
 src/main/scala/diplomacy/Parameters.scala    |  4 ++++
 src/main/scala/uncore/tilelink2/Buffer.scala | 18 +++++-------------
 2 files changed, 9 insertions(+), 13 deletions(-)

diff --git a/src/main/scala/diplomacy/Parameters.scala b/src/main/scala/diplomacy/Parameters.scala
index 0b42dbf4..d4172106 100644
--- a/src/main/scala/diplomacy/Parameters.scala
+++ b/src/main/scala/diplomacy/Parameters.scala
@@ -248,6 +248,10 @@ case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
   require (depth >= 0, "Buffer depth must be >= 0")
   def isDefined = depth > 0
   def latency = if (isDefined && !flow) 1 else 0
+
+  def apply[T <: Data](x: DecoupledIO[T]) =
+    if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
+    else x
 }
 
 object BufferParams
diff --git a/src/main/scala/uncore/tilelink2/Buffer.scala b/src/main/scala/uncore/tilelink2/Buffer.scala
index 32b80cb5..2bc2c067 100644
--- a/src/main/scala/uncore/tilelink2/Buffer.scala
+++ b/src/main/scala/uncore/tilelink2/Buffer.scala
@@ -29,22 +29,14 @@ class TLBuffer(
       val out = node.bundleOut
     }
 
-    def buffer[T <: Data](config: BufferParams, data: DecoupledIO[T]): DecoupledIO[T] = {
-      if (config.isDefined) {
-        Queue(data, config.depth, pipe=config.pipe, flow=config.flow)
-      } else {
-        data
-      }
-    }
-
     ((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
-      out.a <> buffer(a, in .a)
-      in .d <> buffer(d, out.d)
+      out.a <> a(in .a)
+      in .d <> d(out.d)
 
       if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
-        in .b <> buffer(b, out.b)
-        out.c <> buffer(c, in .c)
-        out.e <> buffer(e, in .e)
+        in .b <> b(out.b)
+        out.c <> c(in .c)
+        out.e <> e(in .e)
       } else {
         in.b.valid := Bool(false)
         in.c.ready := Bool(true)

From 1f8c4ba4ca3cb9f7ebb9aa1cf22a7420ef5dd846 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Wed, 14 Jun 2017 14:27:23 -0700
Subject: [PATCH 2/2] CoreplexNetwork: don't force a buffer on the coherence
 manager

Let the l2Config.coherenceManager create its own appropriate buffers.
This can matter if you need to make sure the buffer is in the right
place in the hierarchy for hierarchical place and route.
---
 src/main/scala/coreplex/CoreplexNetwork.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/coreplex/CoreplexNetwork.scala b/src/main/scala/coreplex/CoreplexNetwork.scala
index 66616078..4b88a09d 100644
--- a/src/main/scala/coreplex/CoreplexNetwork.scala
+++ b/src/main/scala/coreplex/CoreplexNetwork.scala
@@ -173,7 +173,7 @@ trait BankedL2CoherenceManagers extends CoreplexNetwork {
     val node = TLOutputNode()
     for (bank <- 0 until l2Config.nBanksPerChannel) {
       val offset = (bank * l2Config.nMemoryChannels) + channel
-      in := TLBuffer(BufferParams.flow, BufferParams.none)(l1tol2.node)
+      in := l1tol2.node
       node := TLFilter(AddressSet(offset * l1tol2_lineBytes, mask))(out)
     }
     node