riscv/rocket-chip
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coreplex: rename RocketPlex => RocketTiles

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This commit is contained in:
Wesley W. Terpstra 2016-11-22 15:49:06 -08:00
parent bbabcf67ff
commit c230580157
2 changed files with 20 additions and 20 deletions
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12
src/main/scala/coreplex/Coreplex.scala
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@ -14,30 +14,30 @@ import rocket._
class DefaultCoreplex(implicit p: Parameters) extends BaseCoreplex class DefaultCoreplex(implicit p: Parameters) extends BaseCoreplex
with CoreplexRISCVPlatform with CoreplexRISCVPlatform
with RocketPlex { with RocketTiles {
override lazy val module = new DefaultCoreplexModule(this, () => new DefaultCoreplexBundle(this)) override lazy val module = new DefaultCoreplexModule(this, () => new DefaultCoreplexBundle(this))
} }
class DefaultCoreplexBundle[+L <: DefaultCoreplex](_outer: L) extends BaseCoreplexBundle(_outer) class DefaultCoreplexBundle[+L <: DefaultCoreplex](_outer: L) extends BaseCoreplexBundle(_outer)
with CoreplexRISCVPlatformBundle with CoreplexRISCVPlatformBundle
with RocketPlexBundle with RocketTilesBundle
class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io) class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io)
with CoreplexRISCVPlatformModule with CoreplexRISCVPlatformModule
with RocketPlexModule with RocketTilesModule
///// /////
class MultiClockCoreplex(implicit p: Parameters) extends BaseCoreplex class MultiClockCoreplex(implicit p: Parameters) extends BaseCoreplex
with CoreplexRISCVPlatform with CoreplexRISCVPlatform
with AsyncRocketPlex { with AsyncRocketTiles {
override lazy val module = new MultiClockCoreplexModule(this, () => new MultiClockCoreplexBundle(this)) override lazy val module = new MultiClockCoreplexModule(this, () => new MultiClockCoreplexBundle(this))
} }
class MultiClockCoreplexBundle[+L <: MultiClockCoreplex](_outer: L) extends BaseCoreplexBundle(_outer) class MultiClockCoreplexBundle[+L <: MultiClockCoreplex](_outer: L) extends BaseCoreplexBundle(_outer)
with CoreplexRISCVPlatformBundle with CoreplexRISCVPlatformBundle
with AsyncRocketPlexBundle with AsyncRocketTilesBundle
class MultiClockCoreplexModule[+L <: MultiClockCoreplex, +B <: MultiClockCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io) class MultiClockCoreplexModule[+L <: MultiClockCoreplex, +B <: MultiClockCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io)
with CoreplexRISCVPlatformModule with CoreplexRISCVPlatformModule
with AsyncRocketPlexModule with AsyncRocketTilesModule

28
src/main/scala/coreplex/RocketPlex.scala → src/main/scala/coreplex/RocketTiles.scala
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@ -8,8 +8,8 @@ import uncore.coherence._
import rocket._ import rocket._
import uncore.devices.NTiles import uncore.devices.NTiles
trait RocketPlex extends CoreplexRISCVPlatform { trait RocketTiles extends CoreplexRISCVPlatform {
val module: RocketPlexModule val module: RocketTilesModule
val rocketTiles = List.tabulate(p(NTiles)) { i => LazyModule(new RocketTile(i)) } val rocketTiles = List.tabulate(p(NTiles)) { i => LazyModule(new RocketTile(i)) }
val tileIntNodes = rocketTiles.map { _ => IntInternalOutputNode() } val tileIntNodes = rocketTiles.map { _ => IntInternalOutputNode() }
@ -22,13 +22,13 @@ trait RocketPlex extends CoreplexRISCVPlatform {
} }
} }
trait RocketPlexBundle extends CoreplexRISCVPlatformBundle { trait RocketTilesBundle extends CoreplexRISCVPlatformBundle {
val outer: CoreplexRISCVPlatform val outer: RocketTiles
} }
trait RocketPlexModule extends CoreplexRISCVPlatformModule { trait RocketTilesModule extends CoreplexRISCVPlatformModule {
val outer: RocketPlex val outer: RocketTiles
val io: RocketPlexBundle val io: RocketTilesBundle
outer.rocketTiles.map(_.module).zipWithIndex.foreach { case (tile, i) => outer.rocketTiles.map(_.module).zipWithIndex.foreach { case (tile, i) =>
tile.io.hartid := UInt(i) tile.io.hartid := UInt(i)
@ -67,8 +67,8 @@ class AsyncRocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
} }
} }
trait AsyncRocketPlex extends CoreplexRISCVPlatform { trait AsyncRocketTiles extends CoreplexRISCVPlatform {
val module: AsyncRocketPlexModule val module: AsyncRocketTilesModule
val rocketTiles = List.tabulate(p(NTiles)) { i => LazyModule(new AsyncRocketTile(i)) } val rocketTiles = List.tabulate(p(NTiles)) { i => LazyModule(new AsyncRocketTile(i)) }
val tileIntNodes = rocketTiles.map { _ => IntInternalOutputNode() } val tileIntNodes = rocketTiles.map { _ => IntInternalOutputNode() }
@ -81,8 +81,8 @@ trait AsyncRocketPlex extends CoreplexRISCVPlatform {
} }
} }
trait AsyncRocketPlexBundle extends CoreplexRISCVPlatformBundle { trait AsyncRocketTilesBundle extends CoreplexRISCVPlatformBundle {
val outer: CoreplexRISCVPlatform val outer: AsyncRocketTiles
val tcrs = Vec(nTiles, new Bundle { val tcrs = Vec(nTiles, new Bundle {
val clock = Clock(INPUT) val clock = Clock(INPUT)
@ -90,9 +90,9 @@ trait AsyncRocketPlexBundle extends CoreplexRISCVPlatformBundle {
}) })
} }
trait AsyncRocketPlexModule extends CoreplexRISCVPlatformModule { trait AsyncRocketTilesModule extends CoreplexRISCVPlatformModule {
val outer: AsyncRocketPlex val outer: AsyncRocketTiles
val io: AsyncRocketPlexBundle val io: AsyncRocketTilesBundle
outer.rocketTiles.map(_.module).zipWithIndex.foreach { case (tile, i) => outer.rocketTiles.map(_.module).zipWithIndex.foreach { case (tile, i) =>
tile.clock := io.tcrs(i).clock tile.clock := io.tcrs(i).clock