From c230580157edeff5fa3e9f1e087c22c193d3e144 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Tue, 22 Nov 2016 15:49:06 -0800 Subject: [PATCH] coreplex: rename RocketPlex => RocketTiles --- src/main/scala/coreplex/Coreplex.scala | 12 ++++---- .../{RocketPlex.scala => RocketTiles.scala} | 28 +++++++++---------- 2 files changed, 20 insertions(+), 20 deletions(-) rename src/main/scala/coreplex/{RocketPlex.scala => RocketTiles.scala} (83%) diff --git a/src/main/scala/coreplex/Coreplex.scala b/src/main/scala/coreplex/Coreplex.scala index fd6fde18..f577338a 100644 --- a/src/main/scala/coreplex/Coreplex.scala +++ b/src/main/scala/coreplex/Coreplex.scala @@ -14,30 +14,30 @@ import rocket._ class DefaultCoreplex(implicit p: Parameters) extends BaseCoreplex with CoreplexRISCVPlatform - with RocketPlex { + with RocketTiles { override lazy val module = new DefaultCoreplexModule(this, () => new DefaultCoreplexBundle(this)) } class DefaultCoreplexBundle[+L <: DefaultCoreplex](_outer: L) extends BaseCoreplexBundle(_outer) with CoreplexRISCVPlatformBundle - with RocketPlexBundle + with RocketTilesBundle class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io) with CoreplexRISCVPlatformModule - with RocketPlexModule + with RocketTilesModule ///// class MultiClockCoreplex(implicit p: Parameters) extends BaseCoreplex with CoreplexRISCVPlatform - with AsyncRocketPlex { + with AsyncRocketTiles { override lazy val module = new MultiClockCoreplexModule(this, () => new MultiClockCoreplexBundle(this)) } class MultiClockCoreplexBundle[+L <: MultiClockCoreplex](_outer: L) extends BaseCoreplexBundle(_outer) with CoreplexRISCVPlatformBundle - with AsyncRocketPlexBundle + with AsyncRocketTilesBundle class MultiClockCoreplexModule[+L <: MultiClockCoreplex, +B <: MultiClockCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io) with CoreplexRISCVPlatformModule - with AsyncRocketPlexModule + with AsyncRocketTilesModule diff --git a/src/main/scala/coreplex/RocketPlex.scala b/src/main/scala/coreplex/RocketTiles.scala similarity index 83% rename from src/main/scala/coreplex/RocketPlex.scala rename to src/main/scala/coreplex/RocketTiles.scala index 5c85112e..78a1097a 100644 --- a/src/main/scala/coreplex/RocketPlex.scala +++ b/src/main/scala/coreplex/RocketTiles.scala @@ -8,8 +8,8 @@ import uncore.coherence._ import rocket._ import uncore.devices.NTiles -trait RocketPlex extends CoreplexRISCVPlatform { - val module: RocketPlexModule +trait RocketTiles extends CoreplexRISCVPlatform { + val module: RocketTilesModule val rocketTiles = List.tabulate(p(NTiles)) { i => LazyModule(new RocketTile(i)) } val tileIntNodes = rocketTiles.map { _ => IntInternalOutputNode() } @@ -22,13 +22,13 @@ trait RocketPlex extends CoreplexRISCVPlatform { } } -trait RocketPlexBundle extends CoreplexRISCVPlatformBundle { - val outer: CoreplexRISCVPlatform +trait RocketTilesBundle extends CoreplexRISCVPlatformBundle { + val outer: RocketTiles } -trait RocketPlexModule extends CoreplexRISCVPlatformModule { - val outer: RocketPlex - val io: RocketPlexBundle +trait RocketTilesModule extends CoreplexRISCVPlatformModule { + val outer: RocketTiles + val io: RocketTilesBundle outer.rocketTiles.map(_.module).zipWithIndex.foreach { case (tile, i) => tile.io.hartid := UInt(i) @@ -67,8 +67,8 @@ class AsyncRocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule { } } -trait AsyncRocketPlex extends CoreplexRISCVPlatform { - val module: AsyncRocketPlexModule +trait AsyncRocketTiles extends CoreplexRISCVPlatform { + val module: AsyncRocketTilesModule val rocketTiles = List.tabulate(p(NTiles)) { i => LazyModule(new AsyncRocketTile(i)) } val tileIntNodes = rocketTiles.map { _ => IntInternalOutputNode() } @@ -81,8 +81,8 @@ trait AsyncRocketPlex extends CoreplexRISCVPlatform { } } -trait AsyncRocketPlexBundle extends CoreplexRISCVPlatformBundle { - val outer: CoreplexRISCVPlatform +trait AsyncRocketTilesBundle extends CoreplexRISCVPlatformBundle { + val outer: AsyncRocketTiles val tcrs = Vec(nTiles, new Bundle { val clock = Clock(INPUT) @@ -90,9 +90,9 @@ trait AsyncRocketPlexBundle extends CoreplexRISCVPlatformBundle { }) } -trait AsyncRocketPlexModule extends CoreplexRISCVPlatformModule { - val outer: AsyncRocketPlex - val io: AsyncRocketPlexBundle +trait AsyncRocketTilesModule extends CoreplexRISCVPlatformModule { + val outer: AsyncRocketTiles + val io: AsyncRocketTilesBundle outer.rocketTiles.map(_.module).zipWithIndex.foreach { case (tile, i) => tile.clock := io.tcrs(i).clock