From c152962642b84b808a5f097eb9351745a17a9334 Mon Sep 17 00:00:00 2001 From: pentin-as <30556064+pentin-as@users.noreply.github.com> Date: Tue, 9 Jan 2018 16:06:43 -0500 Subject: [PATCH] Dual-port RAM replaced with single-port RAM for tag_array in HellaCache (#1181) In accordance with https://github.com/freechipsproject/chisel3/issues/752 --- src/main/scala/rocket/HellaCache.scala | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/main/scala/rocket/HellaCache.scala b/src/main/scala/rocket/HellaCache.scala index 2467a670..c2b21e3a 100644 --- a/src/main/scala/rocket/HellaCache.scala +++ b/src/main/scala/rocket/HellaCache.scala @@ -257,11 +257,12 @@ class L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters) val metabits = rstVal.getWidth val tag_array = SeqMem(nSets, Vec(nWays, UInt(width = metabits))) - when (rst || io.write.valid) { + val wen = rst || io.write.valid + when (wen) { tag_array.write(waddr, Vec.fill(nWays)(wdata), wmask) } - io.resp := tag_array.read(io.read.bits.idx, io.read.valid).map(rstVal.fromBits(_)) + io.resp := tag_array.read(io.read.bits.idx, io.read.fire()).map(rstVal.fromBits(_)) - io.read.ready := !rst && !io.write.valid // so really this could be a 6T RAM + io.read.ready := !wen // so really this could be a 6T RAM io.write.ready := !rst }