riscv/rocket-chip
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fix vcmdq full replay logic

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This commit is contained in:
Andrew Waterman
2012-02-15 17:49:12 -08:00
parent 258d050e1b
commit c13524ad3a
2 changed files with 5 additions and 3 deletions
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2
rocket/src/main/scala/consts.scala
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@@ -193,7 +193,7 @@ object Constants
val HAVE_RVC = false val HAVE_RVC = false
val HAVE_FPU = true val HAVE_FPU = true
val HAVE_VEC = false val HAVE_VEC = true
val FPU_N = UFix(0, 1); val FPU_N = UFix(0, 1);
val FPU_Y = if (HAVE_FPU) UFix(1, 1) else FPU_N; val FPU_Y = if (HAVE_FPU) UFix(1, 1) else FPU_N;

6
rocket/src/main/scala/ctrl.scala
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@@ -658,10 +658,12 @@ class rocketCtrl extends Component
mem_reg_replay := replay_ex && !take_pc_wb; mem_reg_replay := replay_ex && !take_pc_wb;
mem_reg_kill := kill_ex; mem_reg_kill := kill_ex;
wb_reg_replay := replay_mem && !take_pc_wb || vec_replay; wb_reg_replay := replay_mem && !take_pc_wb
wb_reg_exception := mem_exception && !take_pc_wb; wb_reg_exception := mem_exception && !take_pc_wb;
wb_reg_cause := mem_cause; wb_reg_cause := mem_cause;
val replay_wb = wb_reg_replay || vec_replay
val wb_badvaddr_wen = wb_reg_exception && ((wb_reg_cause === UFix(10)) || (wb_reg_cause === UFix(11))) val wb_badvaddr_wen = wb_reg_exception && ((wb_reg_cause === UFix(10)) || (wb_reg_cause === UFix(11)))
// write cause to PCR on an exception // write cause to PCR on an exception
@@ -671,7 +673,7 @@ class rocketCtrl extends Component
io.dpath.sel_pc := io.dpath.sel_pc :=
Mux(wb_reg_exception, PC_EVEC, // exception Mux(wb_reg_exception, PC_EVEC, // exception
Mux(wb_reg_replay, PC_WB, // replay Mux(replay_wb, PC_WB, // replay
Mux(wb_reg_eret, PC_PCR, // eret instruction Mux(wb_reg_eret, PC_PCR, // eret instruction
Mux(ex_reg_btb_hit && !br_taken, PC_EX4, // mispredicted not taken branch Mux(ex_reg_btb_hit && !br_taken, PC_EX4, // mispredicted not taken branch
Mux(!ex_reg_btb_hit && br_taken, PC_BR, // mispredicted taken branch Mux(!ex_reg_btb_hit && br_taken, PC_BR, // mispredicted taken branch