From c13524ad3a4ddfd542518bf6fe2d45ee71f68fbe Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 15 Feb 2012 17:49:12 -0800 Subject: [PATCH] fix vcmdq full replay logic --- rocket/src/main/scala/consts.scala | 2 +- rocket/src/main/scala/ctrl.scala | 6 ++++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala index 2905770a..d10093d0 100644 --- a/rocket/src/main/scala/consts.scala +++ b/rocket/src/main/scala/consts.scala @@ -193,7 +193,7 @@ object Constants val HAVE_RVC = false val HAVE_FPU = true - val HAVE_VEC = false + val HAVE_VEC = true val FPU_N = UFix(0, 1); val FPU_Y = if (HAVE_FPU) UFix(1, 1) else FPU_N; diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala index f60278f8..e593dac7 100644 --- a/rocket/src/main/scala/ctrl.scala +++ b/rocket/src/main/scala/ctrl.scala @@ -658,10 +658,12 @@ class rocketCtrl extends Component mem_reg_replay := replay_ex && !take_pc_wb; mem_reg_kill := kill_ex; - wb_reg_replay := replay_mem && !take_pc_wb || vec_replay; + wb_reg_replay := replay_mem && !take_pc_wb wb_reg_exception := mem_exception && !take_pc_wb; wb_reg_cause := mem_cause; + val replay_wb = wb_reg_replay || vec_replay + val wb_badvaddr_wen = wb_reg_exception && ((wb_reg_cause === UFix(10)) || (wb_reg_cause === UFix(11))) // write cause to PCR on an exception @@ -671,7 +673,7 @@ class rocketCtrl extends Component io.dpath.sel_pc := Mux(wb_reg_exception, PC_EVEC, // exception - Mux(wb_reg_replay, PC_WB, // replay + Mux(replay_wb, PC_WB, // replay Mux(wb_reg_eret, PC_PCR, // eret instruction Mux(ex_reg_btb_hit && !br_taken, PC_EX4, // mispredicted not taken branch Mux(!ex_reg_btb_hit && br_taken, PC_BR, // mispredicted taken branch