riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

make sure ID width requirement in TL -> NASTI converter is correct

Browse Source
This commit is contained in:
Howard Mao 2015-10-27 13:25:29 -07:00
parent 9fa4541916
commit c10870a87c
1 changed files with 1 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
uncore/src/main/scala/tilelink.scala
View File

@ -1422,12 +1422,10 @@ class NastiIOTileLinkIOConverter(implicit p: Parameters) extends TLModule()(p)
MT_Q -> UInt(log2Up(tlDataBytes)))) MT_Q -> UInt(log2Up(tlDataBytes))))
val dataBits = tlDataBits*tlDataBeats val dataBits = tlDataBits*tlDataBeats
val dstIdBits = p(LNHeaderBits)
require(tlDataBits == nastiXDataBits, "Data sizes between LLC and MC don't agree") // TODO: remove this restriction require(tlDataBits == nastiXDataBits, "Data sizes between LLC and MC don't agree") // TODO: remove this restriction
require(tlDataBeats < (1 << nastiXLenBits), "Can't have that many beats") require(tlDataBeats < (1 << nastiXLenBits), "Can't have that many beats")
require(dstIdBits + tlClientXactIdBits < nastiXIdBits, "NastiIO converter is going truncate tags: " + dstIdBits + " + " + tlClientXactIdBits + " >= " + nastiXIdBits) require(tlClientXactIdBits <= nastiXIdBits, "NastiIO converter is going truncate tags: " + tlClientXactIdBits + " > " + nastiXIdBits)
val dst_off = dstIdBits + tlClientXactIdBits
val has_data = io.tl.acquire.bits.hasData() val has_data = io.tl.acquire.bits.hasData()
val is_subblock = io.tl.acquire.bits.isSubBlockType() val is_subblock = io.tl.acquire.bits.isSubBlockType()