From c10870a87ced5cbdd27eace24cd32d4e15751f75 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Tue, 27 Oct 2015 13:25:29 -0700 Subject: [PATCH] make sure ID width requirement in TL -> NASTI converter is correct --- uncore/src/main/scala/tilelink.scala | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/uncore/src/main/scala/tilelink.scala b/uncore/src/main/scala/tilelink.scala index 445dea95..9c7bffb3 100644 --- a/uncore/src/main/scala/tilelink.scala +++ b/uncore/src/main/scala/tilelink.scala @@ -1422,12 +1422,10 @@ class NastiIOTileLinkIOConverter(implicit p: Parameters) extends TLModule()(p) MT_Q -> UInt(log2Up(tlDataBytes)))) val dataBits = tlDataBits*tlDataBeats - val dstIdBits = p(LNHeaderBits) require(tlDataBits == nastiXDataBits, "Data sizes between LLC and MC don't agree") // TODO: remove this restriction require(tlDataBeats < (1 << nastiXLenBits), "Can't have that many beats") - require(dstIdBits + tlClientXactIdBits < nastiXIdBits, "NastiIO converter is going truncate tags: " + dstIdBits + " + " + tlClientXactIdBits + " >= " + nastiXIdBits) + require(tlClientXactIdBits <= nastiXIdBits, "NastiIO converter is going truncate tags: " + tlClientXactIdBits + " > " + nastiXIdBits) - val dst_off = dstIdBits + tlClientXactIdBits val has_data = io.tl.acquire.bits.hasData() val is_subblock = io.tl.acquire.bits.isSubBlockType()