riscv/rocket-chip
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coherence mostly works now

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This commit is contained in:
Andrew Waterman
2012-04-10 02:22:45 -07:00
parent 3cdd166153
commit c0ec3794bf
4 changed files with 18 additions and 14 deletions
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rocket/src/main/scala/nbdcache.scala
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@ -826,8 +826,8 @@ class HellaCache(co: CoherencePolicy) extends Component {
(((r_cpu_req_type === MT_W) || (r_cpu_req_type === MT_WU)) && (r_cpu_req_idx(1,0) != Bits(0))) ||
((r_cpu_req_type === MT_D) && (r_cpu_req_idx(2,0) != Bits(0)));
io.cpu.xcpt_ma_ld := r_cpu_req_val_ && r_req_read && misaligned
io.cpu.xcpt_ma_st := r_cpu_req_val_ && r_req_write && misaligned
io.cpu.xcpt_ma_ld := r_cpu_req_val_ && !early_nack && r_req_read && misaligned
io.cpu.xcpt_ma_st := r_cpu_req_val_ && !early_nack && r_req_write && misaligned
// tags
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