Add TileId parameter, generalizing GroundTestId
This usually shouldn't be used in Tiles that are meant to be P&R'd once and multiply instantiated, as their RTL would no longer be homogeneous. However, it is useful for conditionalizing RTL generation for heterogeneous tiles.
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@ -190,7 +190,7 @@ class HellaCacheGenerator(id: Int)
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class GeneratorTest(implicit p: Parameters)
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extends GroundTest()(p) with HasGeneratorParameters {
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val idStart = p(GroundTestKey).take(tileId)
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val idStart = p(GroundTestKey).take(p(TileId))
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.map(settings => settings.cached + settings.uncached)
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.foldLeft(0)(_ + _)
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@ -4,6 +4,7 @@ import Chisel._
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import uncore.tilelink._
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import uncore.converters._
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import junctions._
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import rocket.TileId
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import cde.Parameters
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class NastiGenerator(id: Int)(implicit val p: Parameters) extends Module
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@ -107,7 +108,7 @@ class NastiConverterTest(implicit p: Parameters) extends GroundTest()(p)
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with HasNastiParameters {
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require(tileSettings.uncached == 1 && tileSettings.cached == 0)
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val genId = p(GroundTestKey).take(tileId)
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val genId = p(GroundTestKey).take(p(TileId))
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.map(settings => settings.cached + settings.uncached)
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.foldLeft(0)(_ + _)
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@ -13,7 +13,6 @@ case object BuildGroundTest extends Field[Parameters => GroundTest]
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case class GroundTestTileSettings(
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uncached: Int = 0, cached: Int = 0, ptw: Int = 0, maxXacts: Int = 1)
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case object GroundTestKey extends Field[Seq[GroundTestTileSettings]]
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case object GroundTestId extends Field[Int]
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trait HasGroundTestConstants {
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val timeoutCodeBits = 4
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@ -22,8 +21,7 @@ trait HasGroundTestConstants {
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trait HasGroundTestParameters extends HasAddrMapParameters {
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implicit val p: Parameters
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val tileId = p(GroundTestId)
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val tileSettings = p(GroundTestKey)(tileId)
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val tileSettings = p(GroundTestKey)(p(TileId))
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val nUncached = tileSettings.uncached
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val nCached = tileSettings.cached
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val nPTW = tileSettings.ptw
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@ -613,7 +613,7 @@ class GroundTestTraceGenerator(implicit p: Parameters)
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require(io.mem.size <= 1)
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require(io.cache.size == 1)
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val traceGen = Module(new TraceGenerator(p(GroundTestId)))
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val traceGen = Module(new TraceGenerator(p(TileId)))
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io.cache.head <> traceGen.io.mem
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if (io.mem.size == 1) {
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