From c05ba1e8641446db20396d20f57906352845609f Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 2 Sep 2016 00:05:40 -0700 Subject: [PATCH] Add TileId parameter, generalizing GroundTestId This usually shouldn't be used in Tiles that are meant to be P&R'd once and multiply instantiated, as their RTL would no longer be homogeneous. However, it is useful for conditionalizing RTL generation for heterogeneous tiles. --- src/main/scala/coreplex/Configs.scala | 3 ++- src/main/scala/coreplex/DirectGroundTest.scala | 3 ++- src/main/scala/coreplex/TestConfigs.scala | 7 +++---- src/main/scala/groundtest/Generator.scala | 2 +- src/main/scala/groundtest/NastiTest.scala | 3 ++- src/main/scala/groundtest/Tile.scala | 4 +--- src/main/scala/groundtest/TraceGen.scala | 2 +- src/main/scala/rocket/rocket.scala | 1 + src/main/scala/rocket/tile.scala | 1 + src/main/scala/rocketchip/TestConfigs.scala | 2 +- 10 files changed, 15 insertions(+), 13 deletions(-) diff --git a/src/main/scala/coreplex/Configs.scala b/src/main/scala/coreplex/Configs.scala index 75d6b449..7b8563ce 100644 --- a/src/main/scala/coreplex/Configs.scala +++ b/src/main/scala/coreplex/Configs.scala @@ -94,8 +94,9 @@ class BaseCoreplexConfig extends Config ( TestGeneration.addSuites(rvi.map(_("p"))) TestGeneration.addSuites((if(site(UseVM)) List("v") else List()).flatMap(env => rvu.map(_(env)))) TestGeneration.addSuite(benchmarks) - List.fill(site(NTiles)){ (r: Bool, p: Parameters) => + List.tabulate(site(NTiles)){ i => (r: Bool, p: Parameters) => Module(new RocketTile(resetSignal = r)(p.alterPartial({ + case TileId => i case TLId => "L1toL2" case NUncachedTileLinkPorts => 1 + site(RoccNMemChannels) }))) diff --git a/src/main/scala/coreplex/DirectGroundTest.scala b/src/main/scala/coreplex/DirectGroundTest.scala index 5897e124..98880f15 100644 --- a/src/main/scala/coreplex/DirectGroundTest.scala +++ b/src/main/scala/coreplex/DirectGroundTest.scala @@ -2,6 +2,7 @@ package coreplex import Chisel._ import cde.{Parameters, Field} +import rocket.TileId import groundtest._ import uncore.tilelink._ import uncore.agents._ @@ -19,7 +20,7 @@ class DirectGroundTestCoreplex(topParams: Parameters) extends Coreplex()(topPara require(nTiles == 1) val test = p(BuildGroundTest)(outermostParams.alterPartial({ - case GroundTestId => 0 + case TileId => 0 case CacheName => "L1D" })) require(test.io.cache.size == 0) diff --git a/src/main/scala/coreplex/TestConfigs.scala b/src/main/scala/coreplex/TestConfigs.scala index 4ae403bf..9c291a4c 100644 --- a/src/main/scala/coreplex/TestConfigs.scala +++ b/src/main/scala/coreplex/TestConfigs.scala @@ -158,10 +158,9 @@ class WithPCIeMockupTest extends Config( maxRequests = 128, startAddress = site(GlobalAddrMap)("mem").start) case BuildGroundTest => - (p: Parameters) => { - val id = p(GroundTestId) - if (id == 0) Module(new GeneratorTest()(p)) - else Module(new NastiConverterTest()(p)) + (p: Parameters) => p(TileId) match { + case 0 => Module(new GeneratorTest()(p)) + case 1 => Module(new NastiConverterTest()(p)) } case _ => throw new CDEMatchError }) diff --git a/src/main/scala/groundtest/Generator.scala b/src/main/scala/groundtest/Generator.scala index db839a16..d677ab96 100644 --- a/src/main/scala/groundtest/Generator.scala +++ b/src/main/scala/groundtest/Generator.scala @@ -190,7 +190,7 @@ class HellaCacheGenerator(id: Int) class GeneratorTest(implicit p: Parameters) extends GroundTest()(p) with HasGeneratorParameters { - val idStart = p(GroundTestKey).take(tileId) + val idStart = p(GroundTestKey).take(p(TileId)) .map(settings => settings.cached + settings.uncached) .foldLeft(0)(_ + _) diff --git a/src/main/scala/groundtest/NastiTest.scala b/src/main/scala/groundtest/NastiTest.scala index f3bb5520..eb2c8a23 100644 --- a/src/main/scala/groundtest/NastiTest.scala +++ b/src/main/scala/groundtest/NastiTest.scala @@ -4,6 +4,7 @@ import Chisel._ import uncore.tilelink._ import uncore.converters._ import junctions._ +import rocket.TileId import cde.Parameters class NastiGenerator(id: Int)(implicit val p: Parameters) extends Module @@ -107,7 +108,7 @@ class NastiConverterTest(implicit p: Parameters) extends GroundTest()(p) with HasNastiParameters { require(tileSettings.uncached == 1 && tileSettings.cached == 0) - val genId = p(GroundTestKey).take(tileId) + val genId = p(GroundTestKey).take(p(TileId)) .map(settings => settings.cached + settings.uncached) .foldLeft(0)(_ + _) diff --git a/src/main/scala/groundtest/Tile.scala b/src/main/scala/groundtest/Tile.scala index 58dfafc8..b0b232d9 100644 --- a/src/main/scala/groundtest/Tile.scala +++ b/src/main/scala/groundtest/Tile.scala @@ -13,7 +13,6 @@ case object BuildGroundTest extends Field[Parameters => GroundTest] case class GroundTestTileSettings( uncached: Int = 0, cached: Int = 0, ptw: Int = 0, maxXacts: Int = 1) case object GroundTestKey extends Field[Seq[GroundTestTileSettings]] -case object GroundTestId extends Field[Int] trait HasGroundTestConstants { val timeoutCodeBits = 4 @@ -22,8 +21,7 @@ trait HasGroundTestConstants { trait HasGroundTestParameters extends HasAddrMapParameters { implicit val p: Parameters - val tileId = p(GroundTestId) - val tileSettings = p(GroundTestKey)(tileId) + val tileSettings = p(GroundTestKey)(p(TileId)) val nUncached = tileSettings.uncached val nCached = tileSettings.cached val nPTW = tileSettings.ptw diff --git a/src/main/scala/groundtest/TraceGen.scala b/src/main/scala/groundtest/TraceGen.scala index 249ee99c..d8888304 100644 --- a/src/main/scala/groundtest/TraceGen.scala +++ b/src/main/scala/groundtest/TraceGen.scala @@ -613,7 +613,7 @@ class GroundTestTraceGenerator(implicit p: Parameters) require(io.mem.size <= 1) require(io.cache.size == 1) - val traceGen = Module(new TraceGenerator(p(GroundTestId))) + val traceGen = Module(new TraceGenerator(p(TileId))) io.cache.head <> traceGen.io.mem if (io.mem.size == 1) { diff --git a/src/main/scala/rocket/rocket.scala b/src/main/scala/rocket/rocket.scala index 4c71c4c5..3c4ed21c 100644 --- a/src/main/scala/rocket/rocket.scala +++ b/src/main/scala/rocket/rocket.scala @@ -71,6 +71,7 @@ trait HasCoreParameters extends HasAddrMapParameters { val coreMaxAddrBits = paddrBits max vaddrBitsExtended val nCustomMrwCsrs = p(NCustomMRWCSRs) val nCores = p(NTiles) + val tileId = p(TileId) // fetchWidth doubled, but coreInstBytes halved, for RVC val decodeWidth = fetchWidth / (if (usingCompressed) 2 else 1) diff --git a/src/main/scala/rocket/tile.scala b/src/main/scala/rocket/tile.scala index 64527f7c..bea82e65 100644 --- a/src/main/scala/rocket/tile.scala +++ b/src/main/scala/rocket/tile.scala @@ -12,6 +12,7 @@ import cde.{Parameters, Field} case object BuildRoCC extends Field[Seq[RoccParameters]] case object NCachedTileLinkPorts extends Field[Int] case object NUncachedTileLinkPorts extends Field[Int] +case object TileId extends Field[Int] case class RoccParameters( opcodes: OpcodeSet, diff --git a/src/main/scala/rocketchip/TestConfigs.scala b/src/main/scala/rocketchip/TestConfigs.scala index e4f74938..368bb77a 100644 --- a/src/main/scala/rocketchip/TestConfigs.scala +++ b/src/main/scala/rocketchip/TestConfigs.scala @@ -72,7 +72,7 @@ class WithGroundTest extends Config( (r: Bool, p: Parameters) => { Module(new GroundTestTile(resetSignal = r)(p.alterPartial({ case TLId => "L1toL2" - case GroundTestId => i + case TileId => i case NCachedTileLinkPorts => if(tileSettings.cached > 0) 1 else 0 case NUncachedTileLinkPorts => tileSettings.uncached })))