riscv/rocket-chip
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add option for 2-cycle load-use delay

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This commit is contained in:
Andrew Waterman
2012-11-24 22:01:08 -08:00
parent b514c7b725
commit c036cdc1ea
4 changed files with 9 additions and 6 deletions
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2
rocket/src/main/scala/tile.scala
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@ -9,6 +9,7 @@ import Util._
case class RocketConfiguration(ntiles: Int, co: CoherencePolicyWithUncached,
icache: ICacheConfig, dcache: DCacheConfig,
fpu: Boolean, vec: Boolean,
fastLoadWord: Boolean = true,
fastLoadByte: Boolean = false)
{
val dcacheReqTagBits = 9 // enforce compliance with require()
@ -16,6 +17,7 @@ case class RocketConfiguration(ntiles: Int, co: CoherencePolicyWithUncached,
val nxpr = 32
val nxprbits = log2Up(nxpr)
val rvc = false
if (fastLoadByte) require(fastLoadWord)
}
class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Component(resetSignal)