riscv/rocket-chip
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add option for 2-cycle load-use delay

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This commit is contained in:
Andrew Waterman
2012-11-24 22:01:08 -08:00
parent b514c7b725
commit c036cdc1ea
4 changed files with 9 additions and 6 deletions
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7
rocket/src/main/scala/ctrl.scala
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@@ -676,9 +676,10 @@ class Control(implicit conf: RocketConfiguration) extends Component
fp_data_hazard_ex && (ex_reg_mem_val || ex_reg_fp_val)
// stall for RAW/WAW hazards on LB/LH and mul/div in memory stage.
val mem_mem_cmd_bh = if (conf.fastLoadByte) Bool(false) else
(mem_reg_mem_type === MT_B) || (mem_reg_mem_type === MT_BU) ||
(mem_reg_mem_type === MT_H) || (mem_reg_mem_type === MT_HU)
val mem_mem_cmd_bh =
if (!conf.fastLoadWord) Bool(true)
else if (conf.fastLoadByte) Bool(false)
else AVec(MT_B, MT_BU, MT_H, MT_HU) contains mem_reg_mem_type
val data_hazard_mem = mem_reg_wen &&
(id_raddr1 != UFix(0) && id_renx1 && id_raddr1 === io.dpath.mem_waddr ||
id_raddr2 != UFix(0) && id_renx2 && id_raddr2 === io.dpath.mem_waddr ||