riscv/rocket-chip
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Don't replay from EX stage.

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EX replays are now handled from MEM.  We may move them to WB.
This commit is contained in:
Andrew Waterman
2011-12-09 19:42:58 -08:00
parent 218f63e66e
commit c01e1f1cef
7 changed files with 921 additions and 75 deletions
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4
rocket/src/main/scala/dpath.scala
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@ -135,16 +135,14 @@ class rocketDpath extends Component
btb.io.correct_target := ex_branch_target;
val if_next_pc =
Mux(io.ctrl.sel_pc === PC_4, if_pc_plus4,
Mux(io.ctrl.sel_pc === PC_BTB, if_btb_target,
Mux(io.ctrl.sel_pc === PC_EX, ex_reg_pc,
Mux(io.ctrl.sel_pc === PC_EX4, ex_reg_pc_plus4,
Mux(io.ctrl.sel_pc === PC_BR, ex_branch_target,
Mux(io.ctrl.sel_pc === PC_JR, ex_jr_target.toUFix,
Mux(io.ctrl.sel_pc === PC_PCR, mem_reg_wdata(VADDR_BITS-1,0), // only used for ERET
Mux(io.ctrl.sel_pc === PC_EVEC, pcr.io.evec,
Mux(io.ctrl.sel_pc === PC_MEM, mem_reg_pc,
UFix(0, VADDR_BITS))))))))));
if_pc_plus4))))))); // PC_4
when (!io.ctrl.stallf && io.host.start) {
if_reg_pc <== if_next_pc.toUFix;