riscv/rocket-chip
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Don't replay from EX stage.

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EX replays are now handled from MEM.  We may move them to WB.
This commit is contained in:
Andrew Waterman
2011-12-09 19:42:58 -08:00
parent 218f63e66e
commit c01e1f1cef
7 changed files with 921 additions and 75 deletions
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11
rocket/src/main/scala/consts.scala
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@ -19,13 +19,10 @@ object Constants
val PC_BTB = UFix(1, 4);
val PC_EX4 = UFix(2, 4);
val PC_BR = UFix(3, 4);
val PC_J = UFix(4, 4);
val PC_JR = UFix(5, 4);
val PC_PCR = UFix(6, 4);
val PC_MEM = UFix(7, 4);
val PC_MEM4 = UFix(8, 4);
val PC_EX = UFix(9, 4);
val PC_EVEC = UFix(10, 4);
val PC_JR = UFix(4, 4);
val PC_PCR = UFix(5, 4);
val PC_MEM = UFix(6, 4);
val PC_EVEC = UFix(7, 4);
val KF_Y = UFix(1, 1);
val KF_N = UFix(0, 1);