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tilelink2 RegisterRouter: fix output data glitches

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If a device changes a register while it's being read but not yet accepted,
this an lead to 'data' changing while 'valid' is high. A violation. The
problem is that RegMapper is fundamentally DecoupledIO. So fix it with a
Queue.
This commit is contained in:
Wesley W. Terpstra 2016-10-01 23:55:02 -07:00 committed by Andrew Waterman
parent e0188f8aa4
commit bff0ffa428
1 changed files with 4 additions and 2 deletions
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6
src/main/scala/uncore/tilelink2/RegisterRouter.scala
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@ -37,8 +37,10 @@ class TLRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int =
in.bits.mask := a.bits.mask in.bits.mask := a.bits.mask
in.bits.extra := Cat(edge.addr_lo(a.bits), a.bits.source, a.bits.size) in.bits.extra := Cat(edge.addr_lo(a.bits), a.bits.source, a.bits.size)
// Invoke the register map builder // Invoke the register map builder and make it Irrevocable
val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*) val out = Queue.irrevocable(
RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*),
entries = 1, pipe = true, flow = true)
// No flow control needed // No flow control needed
in.valid := a.valid in.valid := a.valid