diff --git a/src/main/scala/uncore/tilelink2/RegisterRouter.scala b/src/main/scala/uncore/tilelink2/RegisterRouter.scala
index f7b77685..9732af94 100644
--- a/src/main/scala/uncore/tilelink2/RegisterRouter.scala
+++ b/src/main/scala/uncore/tilelink2/RegisterRouter.scala
@@ -37,8 +37,10 @@ class TLRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int =
     in.bits.mask  := a.bits.mask
     in.bits.extra := Cat(edge.addr_lo(a.bits), a.bits.source, a.bits.size)
 
-    // Invoke the register map builder
-    val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*)
+    // Invoke the register map builder and make it Irrevocable
+    val out = Queue.irrevocable(
+      RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*),
+      entries = 1, pipe = true, flow = true)
 
     // No flow control needed
     in.valid  := a.valid