From bff0ffa428aad0d178b698bb3f4a1901f0cfd091 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Sat, 1 Oct 2016 23:55:02 -0700 Subject: [PATCH] tilelink2 RegisterRouter: fix output data glitches If a device changes a register while it's being read but not yet accepted, this an lead to 'data' changing while 'valid' is high. A violation. The problem is that RegMapper is fundamentally DecoupledIO. So fix it with a Queue. --- src/main/scala/uncore/tilelink2/RegisterRouter.scala | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/main/scala/uncore/tilelink2/RegisterRouter.scala b/src/main/scala/uncore/tilelink2/RegisterRouter.scala index f7b77685..9732af94 100644 --- a/src/main/scala/uncore/tilelink2/RegisterRouter.scala +++ b/src/main/scala/uncore/tilelink2/RegisterRouter.scala @@ -37,8 +37,10 @@ class TLRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = in.bits.mask := a.bits.mask in.bits.extra := Cat(edge.addr_lo(a.bits), a.bits.source, a.bits.size) - // Invoke the register map builder - val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*) + // Invoke the register map builder and make it Irrevocable + val out = Queue.irrevocable( + RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*), + entries = 1, pipe = true, flow = true) // No flow control needed in.valid := a.valid