From bf431c0a53fb7eb61c7f2fe47c5004f8a49f136c Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 20 Jun 2017 18:05:08 -0700 Subject: [PATCH] groundtest: fix test ram width --- src/main/scala/groundtest/Coreplex.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/groundtest/Coreplex.scala b/src/main/scala/groundtest/Coreplex.scala index aa2ec4e9..bfd6d887 100644 --- a/src/main/scala/groundtest/Coreplex.scala +++ b/src/main/scala/groundtest/Coreplex.scala @@ -44,7 +44,7 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex { tile_splitter.node :=* fixer.node tiles.foreach { fixer.node :=* _.masterNode } - val pbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, pbusBlockBytes)) + val pbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, pbusBeatBytes)) pbusRAM.node := TLFragmenter(pbusBeatBytes, pbusBlockBytes)(pbus.node) override lazy val module = new GroundTestCoreplexModule(this, () => new GroundTestCoreplexBundle(this))