riscv/rocket-chip
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Vec(Reg) -> Reg(Vec)

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This commit is contained in:
Andrew Waterman
2015-07-15 12:33:46 -07:00
parent a78e28523c
commit be2ff6dec7
6 changed files with 8 additions and 8 deletions
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2
rocket/src/main/scala/nbdcache.scala
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@ -749,7 +749,7 @@ class HellaCache extends L1HellaCacheModule {
val s2_data = Vec.fill(nWays){Bits(width = encRowBits)}
for (w <- 0 until nWays) {
val regs = Vec.fill(rowWords){Reg(Bits(width = encDataBits))}
val regs = Reg(Vec.fill(rowWords){Bits(width = encDataBits)})
val en1 = s1_clk_en && s1_tag_eq_way(w)
for (i <- 0 until regs.size) {
val en = en1 && ((Bool(i == 0) || !Bool(doNarrowRead)) || s1_writeback)