diff --git a/rocket/src/main/scala/btb.scala b/rocket/src/main/scala/btb.scala
index 86f5934b..878b7e09 100644
--- a/rocket/src/main/scala/btb.scala
+++ b/rocket/src/main/scala/btb.scala
@@ -36,7 +36,7 @@ class RAS(nras: Int) {
 
   private val count = Reg(init=UInt(0,log2Up(nras+1)))
   private val pos = Reg(init=UInt(0,log2Up(nras)))
-  private val stack = Vec.fill(nras){Reg(UInt())}
+  private val stack = Reg(Vec.fill(nras){UInt()})
 }
 
 class BHTResp extends Bundle with BTBParameters {
diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala
index 53e23a60..0161da34 100644
--- a/rocket/src/main/scala/dpath.scala
+++ b/rocket/src/main/scala/dpath.scala
@@ -23,9 +23,9 @@ class Datapath extends CoreModule
   val ex_reg_pc = Reg(UInt())
   val ex_reg_inst = Reg(Bits())
   val ex_reg_kill = Reg(Bool())
-  val ex_reg_rs_bypass = Vec.fill(2)(Reg(Bool()))
-  val ex_reg_rs_lsb = Vec.fill(2)(Reg(Bits()))
-  val ex_reg_rs_msb = Vec.fill(2)(Reg(Bits()))
+  val ex_reg_rs_bypass = Reg(Vec.fill(2)(Bool()))
+  val ex_reg_rs_lsb = Reg(Vec.fill(2)(Bits()))
+  val ex_reg_rs_msb = Reg(Vec.fill(2)(Bits()))
 
   // memory definitions
   val mem_reg_pc = Reg(UInt())
diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala
index 91a488cb..0194ba4c 100644
--- a/rocket/src/main/scala/fpu.scala
+++ b/rocket/src/main/scala/fpu.scala
@@ -461,7 +461,7 @@ class FPU extends Module
   val memLatencyMask = latencyMask(mem_ctrl, 2)
 
   val wen = Reg(init=Bits(0, maxLatency-1))
-  val winfo = Vec.fill(maxLatency-1){Reg(Bits())}
+  val winfo = Reg(Vec.fill(maxLatency-1){Bits()})
   val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)
   val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, ex_reg_valid)
   val mem_winfo = Cat(pipeid(mem_ctrl), mem_reg_inst(11,7))
diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala
index 6da75d36..43a30ef5 100644
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@@ -218,7 +218,7 @@ class ICache extends FrontendModule
 
   val s1_tag_match = Vec.fill(nWays){Bool()}
   val s2_tag_hit = Vec.fill(nWays){Bool()}
-  val s2_dout = Vec.fill(nWays){Reg(Bits())}
+  val s2_dout = Reg(Vec.fill(nWays){Bits()})
 
   for (i <- 0 until nWays) {
     val s1_vb = !io.invalidate && vb_array(Cat(UInt(i), s1_pgoff(untagBits-1,blockOffBits))).toBool
diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index 4a24c6e5..0ad6f301 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -749,7 +749,7 @@ class HellaCache extends L1HellaCacheModule {
 
   val s2_data = Vec.fill(nWays){Bits(width = encRowBits)}
   for (w <- 0 until nWays) {
-    val regs = Vec.fill(rowWords){Reg(Bits(width = encDataBits))}
+    val regs = Reg(Vec.fill(rowWords){Bits(width = encDataBits)})
     val en1 = s1_clk_en && s1_tag_eq_way(w)
     for (i <- 0 until regs.size) {
       val en = en1 && ((Bool(i == 0) || !Bool(doNarrowRead)) || s1_writeback)
diff --git a/rocket/src/main/scala/rocc.scala b/rocket/src/main/scala/rocc.scala
index 725a500b..c8838c69 100644
--- a/rocket/src/main/scala/rocc.scala
+++ b/rocket/src/main/scala/rocc.scala
@@ -62,7 +62,7 @@ class AccumulatorExample extends RoCC
 {
   val n = 4
   val regfile = Mem(UInt(width = xLen), n)
-  val busy = Vec.fill(n){Reg(init=Bool(false))}
+  val busy = Reg(init=Vec.fill(n){Bool(false)})
 
   val cmd = Queue(io.cmd)
   val funct = cmd.bits.inst.funct