Vec(Reg) -> Reg(Vec)
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@@ -218,7 +218,7 @@ class ICache extends FrontendModule
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val s1_tag_match = Vec.fill(nWays){Bool()}
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val s2_tag_hit = Vec.fill(nWays){Bool()}
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val s2_dout = Vec.fill(nWays){Reg(Bits())}
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val s2_dout = Reg(Vec.fill(nWays){Bits()})
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for (i <- 0 until nWays) {
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val s1_vb = !io.invalidate && vb_array(Cat(UInt(i), s1_pgoff(untagBits-1,blockOffBits))).toBool
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