refactored vector queue interface
This commit is contained in:
parent
8764fe786a
commit
be1980dd2d
@ -46,10 +46,10 @@ class Core(implicit conf: RocketConfiguration) extends Component
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val vdtlb = new TLB(8)
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val vdtlb = new TLB(8)
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ptw += vdtlb.io.ptw
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ptw += vdtlb.io.ptw
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vdtlb.io <> vu.io.vec_tlb
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vdtlb.io <> vu.io.vtlb
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val pftlb = new TLB(2)
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val pftlb = new TLB(2)
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pftlb.io <> vu.io.vec_pftlb
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pftlb.io <> vu.io.vpftlb
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ptw += pftlb.io.ptw
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ptw += pftlb.io.ptw
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dpath.io.vec_ctrl <> ctrl.io.vec_dpath
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dpath.io.vec_ctrl <> ctrl.io.vec_dpath
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@ -68,44 +68,33 @@ class Core(implicit conf: RocketConfiguration) extends Component
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io.vimem.req.bits.mispredict := Bool(false)
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io.vimem.req.bits.mispredict := Bool(false)
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io.vimem.req.bits.taken := Bool(false)
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io.vimem.req.bits.taken := Bool(false)
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// hooking up vector command queues
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ctrl.io.vec_iface.vcmdq <> vu.io.vcmdq
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vu.io.vec_cmdq.valid := ctrl.io.vec_iface.vcmdq_valid
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ctrl.io.vec_iface.vximm1q <> vu.io.vximm1q
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vu.io.vec_cmdq.bits := dpath.io.vec_iface.vcmdq_bits
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ctrl.io.vec_iface.vximm2q <> vu.io.vximm2q
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vu.io.vec_ximm1q.valid := ctrl.io.vec_iface.vximm1q_valid
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ctrl.io.vec_iface.vcntq <> vu.io.vcntq
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vu.io.vec_ximm1q.bits := dpath.io.vec_iface.vximm1q_bits
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vu.io.vec_ximm2q.valid := ctrl.io.vec_iface.vximm2q_valid
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vu.io.vec_ximm2q.bits := dpath.io.vec_iface.vximm2q_bits
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vu.io.vec_cntq.valid := ctrl.io.vec_iface.vcntq_valid
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vu.io.vec_cntq.bits := Cat(dpath.io.vec_iface.vcntq_last, dpath.io.vec_iface.vcntq_bits)
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// prefetch queues
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dpath.io.vec_iface.vcmdq <> vu.io.vcmdq
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vu.io.vec_pfcmdq.valid := ctrl.io.vec_iface.vpfcmdq_valid
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dpath.io.vec_iface.vximm1q <> vu.io.vximm1q
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vu.io.vec_pfcmdq.bits := dpath.io.vec_iface.vcmdq_bits
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dpath.io.vec_iface.vximm2q <> vu.io.vximm2q
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vu.io.vec_pfximm1q.valid := ctrl.io.vec_iface.vpfximm1q_valid
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dpath.io.vec_iface.vcntq <> vu.io.vcntq
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vu.io.vec_pfximm1q.bits := dpath.io.vec_iface.vximm1q_bits
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vu.io.vec_pfximm2q.valid := ctrl.io.vec_iface.vpfximm2q_valid
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vu.io.vec_pfximm2q.bits := dpath.io.vec_iface.vximm2q_bits
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vu.io.vec_pfcntq.valid := ctrl.io.vec_iface.vpfcntq_valid
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vu.io.vec_pfcntq.bits := dpath.io.vec_iface.vcntq_bits
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// don't have to use pf ready signals
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ctrl.io.vec_iface.vpfcmdq <> vu.io.vpfcmdq
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// if cmdq is not a load or store
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ctrl.io.vec_iface.vpfximm1q <> vu.io.vpfximm1q
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ctrl.io.vec_iface.vcmdq_ready := vu.io.vec_cmdq.ready
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ctrl.io.vec_iface.vpfximm2q <> vu.io.vpfximm2q
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ctrl.io.vec_iface.vximm1q_ready := vu.io.vec_ximm1q.ready
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ctrl.io.vec_iface.vpfcntq <> vu.io.vpfcntq
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ctrl.io.vec_iface.vximm2q_ready := vu.io.vec_ximm2q.ready
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ctrl.io.vec_iface.vcntq_ready := vu.io.vec_cntq.ready
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dpath.io.vec_iface.vpfcmdq <> vu.io.vpfcmdq
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ctrl.io.vec_iface.vpfcmdq_ready := vu.io.vec_pfcmdq.ready
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dpath.io.vec_iface.vpfximm1q <> vu.io.vpfximm1q
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ctrl.io.vec_iface.vpfximm1q_ready := vu.io.vec_pfximm1q.ready
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dpath.io.vec_iface.vpfximm2q <> vu.io.vpfximm2q
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ctrl.io.vec_iface.vpfximm2q_ready := vu.io.vec_pfximm2q.ready
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dpath.io.vec_iface.vpfcntq <> vu.io.vpfcntq
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ctrl.io.vec_iface.vpfcntq_ready := vu.io.vec_pfcntq.ready
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// user level vector command queue ready signals
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// user level vector command queue ready signals
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ctrl.io.vec_iface.vcmdq_user_ready := vu.io.vec_cmdq_user_ready
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ctrl.io.vec_iface.vcmdq_user_ready := vu.io.vcmdq_user_ready
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ctrl.io.vec_iface.vximm1q_user_ready := vu.io.vec_ximm1q_user_ready
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ctrl.io.vec_iface.vximm1q_user_ready := vu.io.vximm1q_user_ready
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ctrl.io.vec_iface.vximm2q_user_ready := vu.io.vec_ximm2q_user_ready
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ctrl.io.vec_iface.vximm2q_user_ready := vu.io.vximm2q_user_ready
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// fences
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// fences
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ctrl.io.vec_iface.vfence_ready := vu.io.vec_fence_ready
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ctrl.io.vec_iface.vfence_ready := vu.io.vfence_ready
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// irqs
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// irqs
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ctrl.io.vec_iface.irq := vu.io.irq
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ctrl.io.vec_iface.irq := vu.io.irq
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@ -437,14 +437,14 @@ class Control(implicit conf: RocketConfiguration) extends Component
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vec_dec.io.inst := io.dpath.inst
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vec_dec.io.inst := io.dpath.inst
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val s = io.dpath.status(SR_S)
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val s = io.dpath.status(SR_S)
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val mask_cmdq_ready = !vec_dec.io.sigs.enq_cmdq || s && io.vec_iface.vcmdq_ready || !s && io.vec_iface.vcmdq_user_ready
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val mask_cmdq_ready = !vec_dec.io.sigs.enq_cmdq || s && io.vec_iface.vcmdq.ready || !s && io.vec_iface.vcmdq_user_ready
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val mask_ximm1q_ready = !vec_dec.io.sigs.enq_ximm1q || s && io.vec_iface.vximm1q_ready || !s && io.vec_iface.vximm1q_user_ready
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val mask_ximm1q_ready = !vec_dec.io.sigs.enq_ximm1q || s && io.vec_iface.vximm1q.ready || !s && io.vec_iface.vximm1q_user_ready
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val mask_ximm2q_ready = !vec_dec.io.sigs.enq_ximm2q || s && io.vec_iface.vximm2q_ready || !s && io.vec_iface.vximm2q_user_ready
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val mask_ximm2q_ready = !vec_dec.io.sigs.enq_ximm2q || s && io.vec_iface.vximm2q.ready || !s && io.vec_iface.vximm2q_user_ready
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val mask_cntq_ready = !vec_dec.io.sigs.enq_cntq || io.vec_iface.vcntq_ready
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val mask_cntq_ready = !vec_dec.io.sigs.enq_cntq || io.vec_iface.vcntq.ready
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val mask_pfcmdq_ready = !vec_dec.io.sigs.enq_pfcmdq || io.vec_iface.vpfcmdq_ready
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val mask_pfcmdq_ready = !vec_dec.io.sigs.enq_pfcmdq || io.vec_iface.vpfcmdq.ready
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val mask_pfximm1q_ready = !vec_dec.io.sigs.enq_pfximm1q || io.vec_iface.vpfximm1q_ready
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val mask_pfximm1q_ready = !vec_dec.io.sigs.enq_pfximm1q || io.vec_iface.vpfximm1q.ready
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val mask_pfximm2q_ready = !vec_dec.io.sigs.enq_pfximm2q || io.vec_iface.vpfximm2q_ready
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val mask_pfximm2q_ready = !vec_dec.io.sigs.enq_pfximm2q || io.vec_iface.vpfximm2q.ready
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val mask_pfcntq_ready = !vec_dec.io.sigs.enq_pfcntq || io.vec_iface.vpfcntq_ready
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val mask_pfcntq_ready = !vec_dec.io.sigs.enq_pfcntq || io.vec_iface.vpfcntq.ready
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vec_stalld =
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vec_stalld =
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id_vec_val && (
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id_vec_val && (
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@ -4,6 +4,7 @@ import Chisel._
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import Node._
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import Node._
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import Constants._
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import Constants._
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import Instructions._
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import Instructions._
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import hwacha.Constants._
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class ioCtrlDpathVec extends Bundle
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class ioCtrlDpathVec extends Bundle
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{
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{
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@ -19,23 +20,15 @@ class ioCtrlDpathVec extends Bundle
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class ioCtrlVecInterface extends Bundle
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class ioCtrlVecInterface extends Bundle
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{
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{
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val vcmdq_valid = Bool(OUTPUT)
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val vcmdq = new FIFOIO()(Bits(width = SZ_VCMD))
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val vcmdq_ready = Bool(INPUT)
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val vximm1q = new FIFOIO()(Bits(width = SZ_VIMM))
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val vximm1q_valid = Bool(OUTPUT)
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val vximm2q = new FIFOIO()(Bits(width = SZ_VSTRIDE))
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val vximm1q_ready = Bool(INPUT)
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val vcntq = new FIFOIO()(Bits(width = SZ_VLEN+1))
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val vximm2q_valid = Bool(OUTPUT)
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val vximm2q_ready = Bool(INPUT)
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val vcntq_valid = Bool(OUTPUT)
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val vcntq_ready = Bool(INPUT)
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val vpfcmdq_valid = Bool(OUTPUT)
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val vpfcmdq = new FIFOIO()(Bits(width = SZ_VCMD))
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val vpfcmdq_ready = Bool(INPUT)
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val vpfximm1q = new FIFOIO()(Bits(width = SZ_VIMM))
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val vpfximm1q_valid = Bool(OUTPUT)
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val vpfximm2q = new FIFOIO()(Bits(width = SZ_VSTRIDE))
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val vpfximm1q_ready = Bool(INPUT)
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val vpfcntq = new FIFOIO()(Bits(width = SZ_VLEN))
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val vpfximm2q_valid = Bool(OUTPUT)
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val vpfximm2q_ready = Bool(INPUT)
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val vpfcntq_valid = Bool(OUTPUT)
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val vpfcntq_ready = Bool(INPUT)
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val vcmdq_user_ready = Bool(INPUT)
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val vcmdq_user_ready = Bool(INPUT)
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val vximm1q_user_ready = Bool(INPUT)
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val vximm1q_user_ready = Bool(INPUT)
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@ -207,14 +200,14 @@ class rocketCtrlVec extends Component
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val enq_pfximm2q_mask_pfq = dec.io.sigs.enq_pfximm2q && (!dec.io.sigs.pfaq || io.dpath.pfq)
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val enq_pfximm2q_mask_pfq = dec.io.sigs.enq_pfximm2q && (!dec.io.sigs.pfaq || io.dpath.pfq)
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val enq_pfcntq_mask_pfq = dec.io.sigs.enq_pfcntq && (!dec.io.sigs.pfaq || io.dpath.pfq)
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val enq_pfcntq_mask_pfq = dec.io.sigs.enq_pfcntq && (!dec.io.sigs.pfaq || io.dpath.pfq)
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val mask_cmdq_ready = !dec.io.sigs.enq_cmdq || io.s && io.iface.vcmdq_ready || !io.s && io.iface.vcmdq_user_ready
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val mask_cmdq_ready = !dec.io.sigs.enq_cmdq || io.s && io.iface.vcmdq.ready || !io.s && io.iface.vcmdq_user_ready
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val mask_ximm1q_ready = !dec.io.sigs.enq_ximm1q || io.s && io.iface.vximm1q_ready || !io.s && io.iface.vximm1q_user_ready
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val mask_ximm1q_ready = !dec.io.sigs.enq_ximm1q || io.s && io.iface.vximm1q.ready || !io.s && io.iface.vximm1q_user_ready
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val mask_ximm2q_ready = !dec.io.sigs.enq_ximm2q || io.s && io.iface.vximm2q_ready || !io.s && io.iface.vximm2q_user_ready
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val mask_ximm2q_ready = !dec.io.sigs.enq_ximm2q || io.s && io.iface.vximm2q.ready || !io.s && io.iface.vximm2q_user_ready
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val mask_cntq_ready = !dec.io.sigs.enq_cntq || io.iface.vcntq_ready
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val mask_cntq_ready = !dec.io.sigs.enq_cntq || io.iface.vcntq.ready
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val mask_pfcmdq_ready = !enq_pfcmdq_mask_pfq || io.iface.vpfcmdq_ready
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val mask_pfcmdq_ready = !enq_pfcmdq_mask_pfq || io.iface.vpfcmdq.ready
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val mask_pfximm1q_ready = !enq_pfximm1q_mask_pfq || io.iface.vpfximm1q_ready
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val mask_pfximm1q_ready = !enq_pfximm1q_mask_pfq || io.iface.vpfximm1q.ready
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val mask_pfximm2q_ready = !enq_pfximm2q_mask_pfq || io.iface.vpfximm2q_ready
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val mask_pfximm2q_ready = !enq_pfximm2q_mask_pfq || io.iface.vpfximm2q.ready
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val mask_pfcntq_ready = !enq_pfcntq_mask_pfq || io.iface.vpfcntq_ready
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val mask_pfcntq_ready = !enq_pfcntq_mask_pfq || io.iface.vpfcntq.ready
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io.dpath.wen := dec.io.sigs.wen
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io.dpath.wen := dec.io.sigs.wen
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io.dpath.fn := dec.io.sigs.fn
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io.dpath.fn := dec.io.sigs.fn
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@ -222,42 +215,42 @@ class rocketCtrlVec extends Component
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io.dpath.sel_vimm := dec.io.sigs.sel_vimm
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io.dpath.sel_vimm := dec.io.sigs.sel_vimm
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io.dpath.sel_vimm2 := dec.io.sigs.sel_vimm2
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io.dpath.sel_vimm2 := dec.io.sigs.sel_vimm2
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io.iface.vcmdq_valid :=
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io.iface.vcmdq.valid :=
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valid_common &&
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valid_common &&
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dec.io.sigs.enq_cmdq && mask_ximm1q_ready && mask_ximm2q_ready && mask_cntq_ready &&
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dec.io.sigs.enq_cmdq && mask_ximm1q_ready && mask_ximm2q_ready && mask_cntq_ready &&
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mask_pfcmdq_ready && mask_pfximm1q_ready && mask_pfximm2q_ready && mask_pfcntq_ready
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mask_pfcmdq_ready && mask_pfximm1q_ready && mask_pfximm2q_ready && mask_pfcntq_ready
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io.iface.vximm1q_valid :=
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io.iface.vximm1q.valid :=
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valid_common &&
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valid_common &&
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mask_cmdq_ready && dec.io.sigs.enq_ximm1q && mask_ximm2q_ready && mask_cntq_ready &&
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mask_cmdq_ready && dec.io.sigs.enq_ximm1q && mask_ximm2q_ready && mask_cntq_ready &&
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mask_pfcmdq_ready && mask_pfximm1q_ready && mask_pfximm2q_ready && mask_pfcntq_ready
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mask_pfcmdq_ready && mask_pfximm1q_ready && mask_pfximm2q_ready && mask_pfcntq_ready
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io.iface.vximm2q_valid :=
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io.iface.vximm2q.valid :=
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valid_common &&
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valid_common &&
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mask_cmdq_ready && mask_ximm1q_ready && dec.io.sigs.enq_ximm2q && mask_cntq_ready &&
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mask_cmdq_ready && mask_ximm1q_ready && dec.io.sigs.enq_ximm2q && mask_cntq_ready &&
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mask_pfcmdq_ready && mask_pfximm1q_ready && mask_pfximm2q_ready && mask_pfcntq_ready
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mask_pfcmdq_ready && mask_pfximm1q_ready && mask_pfximm2q_ready && mask_pfcntq_ready
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io.iface.vcntq_valid :=
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io.iface.vcntq.valid :=
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valid_common &&
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valid_common &&
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mask_cmdq_ready && mask_ximm1q_ready && mask_ximm2q_ready && dec.io.sigs.enq_cntq &&
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mask_cmdq_ready && mask_ximm1q_ready && mask_ximm2q_ready && dec.io.sigs.enq_cntq &&
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mask_pfcmdq_ready && mask_pfximm1q_ready && mask_pfximm2q_ready && mask_pfcntq_ready
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mask_pfcmdq_ready && mask_pfximm1q_ready && mask_pfximm2q_ready && mask_pfcntq_ready
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io.iface.vpfcmdq_valid :=
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io.iface.vpfcmdq.valid :=
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valid_common &&
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valid_common &&
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mask_cmdq_ready && mask_ximm1q_ready && mask_ximm2q_ready && mask_cntq_ready &&
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mask_cmdq_ready && mask_ximm1q_ready && mask_ximm2q_ready && mask_cntq_ready &&
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enq_pfcmdq_mask_pfq && mask_pfximm1q_ready && mask_pfximm2q_ready && mask_pfcntq_ready
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enq_pfcmdq_mask_pfq && mask_pfximm1q_ready && mask_pfximm2q_ready && mask_pfcntq_ready
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io.iface.vpfximm1q_valid :=
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io.iface.vpfximm1q.valid :=
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valid_common &&
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valid_common &&
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mask_cmdq_ready && mask_ximm1q_ready && mask_ximm2q_ready && mask_cntq_ready &&
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mask_cmdq_ready && mask_ximm1q_ready && mask_ximm2q_ready && mask_cntq_ready &&
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mask_pfcmdq_ready && enq_pfximm1q_mask_pfq && mask_pfximm2q_ready && mask_pfcntq_ready
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mask_pfcmdq_ready && enq_pfximm1q_mask_pfq && mask_pfximm2q_ready && mask_pfcntq_ready
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io.iface.vpfximm2q_valid :=
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io.iface.vpfximm2q.valid :=
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valid_common &&
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valid_common &&
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mask_cmdq_ready && mask_ximm1q_ready && mask_ximm2q_ready && mask_cntq_ready &&
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mask_cmdq_ready && mask_ximm1q_ready && mask_ximm2q_ready && mask_cntq_ready &&
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mask_pfcmdq_ready && mask_pfximm1q_ready && enq_pfximm2q_mask_pfq && mask_pfcntq_ready
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mask_pfcmdq_ready && mask_pfximm1q_ready && enq_pfximm2q_mask_pfq && mask_pfcntq_ready
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io.iface.vpfcntq_valid :=
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io.iface.vpfcntq.valid :=
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valid_common &&
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valid_common &&
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mask_cmdq_ready && mask_ximm1q_ready && mask_ximm2q_ready && mask_cntq_ready &&
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mask_cmdq_ready && mask_ximm1q_ready && mask_ximm2q_ready && mask_cntq_ready &&
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mask_pfcmdq_ready && mask_pfximm1q_ready && mask_pfximm2q_ready && enq_pfcntq_mask_pfq
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mask_pfcmdq_ready && mask_pfximm1q_ready && mask_pfximm2q_ready && enq_pfcntq_mask_pfq
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@ -8,11 +8,16 @@ import hwacha.Constants._
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class ioDpathVecInterface extends Bundle
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class ioDpathVecInterface extends Bundle
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{
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{
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val vcmdq_bits = Bits(OUTPUT, SZ_VCMD)
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val vcmdq = new FIFOIO()(Bits(width = SZ_VCMD))
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val vximm1q_bits = Bits(OUTPUT, SZ_VIMM)
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val vximm1q = new FIFOIO()(Bits(width = SZ_VIMM))
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val vximm2q_bits = Bits(OUTPUT, SZ_VSTRIDE)
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val vximm2q = new FIFOIO()(Bits(width = SZ_VSTRIDE))
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val vcntq_bits = Bits(OUTPUT, SZ_VLEN)
|
val vcntq = new FIFOIO()(Bits(width = SZ_VLEN+1))
|
||||||
val vcntq_last = Bool(OUTPUT)
|
|
||||||
|
val vpfcmdq = new FIFOIO()(Bits(width = SZ_VCMD))
|
||||||
|
val vpfximm1q = new FIFOIO()(Bits(width = SZ_VIMM))
|
||||||
|
val vpfximm2q = new FIFOIO()(Bits(width = SZ_VSTRIDE))
|
||||||
|
val vpfcntq = new FIFOIO()(Bits(width = SZ_VLEN))
|
||||||
|
|
||||||
val evac_addr = Bits(OUTPUT, 64)
|
val evac_addr = Bits(OUTPUT, 64)
|
||||||
val irq_aux = Bits(INPUT, 64)
|
val irq_aux = Bits(INPUT, 64)
|
||||||
}
|
}
|
||||||
@ -147,7 +152,7 @@ class rocketDpathVec extends Component
|
|||||||
|
|
||||||
val appvlm1 = appvl - UFix(1)
|
val appvlm1 = appvl - UFix(1)
|
||||||
|
|
||||||
io.iface.vcmdq_bits :=
|
io.iface.vcmdq.bits :=
|
||||||
Mux(io.ctrl.sel_vcmd === VCMD_I, Cat(Bits(0,2), Bits(0,4), io.inst(9,8), Bits(0,6), Bits(0,6)),
|
Mux(io.ctrl.sel_vcmd === VCMD_I, Cat(Bits(0,2), Bits(0,4), io.inst(9,8), Bits(0,6), Bits(0,6)),
|
||||||
Mux(io.ctrl.sel_vcmd === VCMD_F, Cat(Bits(0,2), Bits(1,3), io.inst(9,7), Bits(0,6), Bits(0,6)),
|
Mux(io.ctrl.sel_vcmd === VCMD_F, Cat(Bits(0,2), Bits(1,3), io.inst(9,7), Bits(0,6), Bits(0,6)),
|
||||||
Mux(io.ctrl.sel_vcmd === VCMD_TX, Cat(Bits(1,2), io.inst(13,8), Bits(0,1), io.waddr, Bits(0,1), io.raddr1),
|
Mux(io.ctrl.sel_vcmd === VCMD_TX, Cat(Bits(1,2), io.inst(13,8), Bits(0,1), io.waddr, Bits(0,1), io.raddr1),
|
||||||
@ -157,16 +162,21 @@ class rocketDpathVec extends Component
|
|||||||
Mux(io.ctrl.sel_vcmd === VCMD_A, io.wdata(SZ_VCMD-1, 0),
|
Mux(io.ctrl.sel_vcmd === VCMD_A, io.wdata(SZ_VCMD-1, 0),
|
||||||
Bits(0,20))))))))
|
Bits(0,20))))))))
|
||||||
|
|
||||||
io.iface.vximm1q_bits :=
|
io.iface.vximm1q.bits :=
|
||||||
Mux(io.ctrl.sel_vimm === VIMM_VLEN, Cat(Bits(0,29), io.vecbankcnt, io.vecbank, nfregs(5,0), nxregs(5,0), appvlm1(10,0)),
|
Mux(io.ctrl.sel_vimm === VIMM_VLEN, Cat(Bits(0,29), io.vecbankcnt, io.vecbank, nfregs(5,0), nxregs(5,0), appvlm1(10,0)),
|
||||||
io.wdata) // VIMM_ALU
|
io.wdata) // VIMM_ALU
|
||||||
|
|
||||||
io.iface.vximm2q_bits :=
|
io.iface.vximm2q.bits :=
|
||||||
Mux(io.ctrl.sel_vimm2 === VIMM2_RS2, io.rs2,
|
Mux(io.ctrl.sel_vimm2 === VIMM2_RS2, io.rs2,
|
||||||
io.wdata) // VIMM2_ALU
|
io.wdata) // VIMM2_ALU
|
||||||
|
|
||||||
io.iface.vcntq_bits := io.wdata(SZ_VLEN-1, 0)
|
val last = io.rs2(1)
|
||||||
io.iface.vcntq_last := io.rs2(1)
|
io.iface.vcntq.bits := Cat(last, io.iface.vpfcntq.bits)
|
||||||
|
|
||||||
|
io.iface.vpfcmdq.bits := io.iface.vcmdq.bits
|
||||||
|
io.iface.vpfximm1q.bits := io.iface.vximm1q.bits
|
||||||
|
io.iface.vpfximm2q.bits := io.iface.vximm2q.bits
|
||||||
|
io.iface.vpfcntq.bits := io.wdata(SZ_VLEN-1, 0)
|
||||||
|
|
||||||
io.iface.evac_addr := io.wdata
|
io.iface.evac_addr := io.wdata
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user