From be1980dd2d3ffd722dcaf4ad56fd71f5f5dda831 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Wed, 7 Nov 2012 01:15:33 -0800 Subject: [PATCH] refactored vector queue interface --- rocket/src/main/scala/core.scala | 57 +++++++++++---------------- rocket/src/main/scala/ctrl.scala | 16 ++++---- rocket/src/main/scala/ctrl_vec.scala | 57 ++++++++++++--------------- rocket/src/main/scala/dpath_vec.scala | 30 +++++++++----- 4 files changed, 76 insertions(+), 84 deletions(-) diff --git a/rocket/src/main/scala/core.scala b/rocket/src/main/scala/core.scala index 9ef40699..8cb6bc43 100644 --- a/rocket/src/main/scala/core.scala +++ b/rocket/src/main/scala/core.scala @@ -46,10 +46,10 @@ class Core(implicit conf: RocketConfiguration) extends Component val vdtlb = new TLB(8) ptw += vdtlb.io.ptw - vdtlb.io <> vu.io.vec_tlb + vdtlb.io <> vu.io.vtlb val pftlb = new TLB(2) - pftlb.io <> vu.io.vec_pftlb + pftlb.io <> vu.io.vpftlb ptw += pftlb.io.ptw dpath.io.vec_ctrl <> ctrl.io.vec_dpath @@ -68,44 +68,33 @@ class Core(implicit conf: RocketConfiguration) extends Component io.vimem.req.bits.mispredict := Bool(false) io.vimem.req.bits.taken := Bool(false) - // hooking up vector command queues - vu.io.vec_cmdq.valid := ctrl.io.vec_iface.vcmdq_valid - vu.io.vec_cmdq.bits := dpath.io.vec_iface.vcmdq_bits - vu.io.vec_ximm1q.valid := ctrl.io.vec_iface.vximm1q_valid - vu.io.vec_ximm1q.bits := dpath.io.vec_iface.vximm1q_bits - vu.io.vec_ximm2q.valid := ctrl.io.vec_iface.vximm2q_valid - vu.io.vec_ximm2q.bits := dpath.io.vec_iface.vximm2q_bits - vu.io.vec_cntq.valid := ctrl.io.vec_iface.vcntq_valid - vu.io.vec_cntq.bits := Cat(dpath.io.vec_iface.vcntq_last, dpath.io.vec_iface.vcntq_bits) + ctrl.io.vec_iface.vcmdq <> vu.io.vcmdq + ctrl.io.vec_iface.vximm1q <> vu.io.vximm1q + ctrl.io.vec_iface.vximm2q <> vu.io.vximm2q + ctrl.io.vec_iface.vcntq <> vu.io.vcntq - // prefetch queues - vu.io.vec_pfcmdq.valid := ctrl.io.vec_iface.vpfcmdq_valid - vu.io.vec_pfcmdq.bits := dpath.io.vec_iface.vcmdq_bits - vu.io.vec_pfximm1q.valid := ctrl.io.vec_iface.vpfximm1q_valid - vu.io.vec_pfximm1q.bits := dpath.io.vec_iface.vximm1q_bits - vu.io.vec_pfximm2q.valid := ctrl.io.vec_iface.vpfximm2q_valid - vu.io.vec_pfximm2q.bits := dpath.io.vec_iface.vximm2q_bits - vu.io.vec_pfcntq.valid := ctrl.io.vec_iface.vpfcntq_valid - vu.io.vec_pfcntq.bits := dpath.io.vec_iface.vcntq_bits + dpath.io.vec_iface.vcmdq <> vu.io.vcmdq + dpath.io.vec_iface.vximm1q <> vu.io.vximm1q + dpath.io.vec_iface.vximm2q <> vu.io.vximm2q + dpath.io.vec_iface.vcntq <> vu.io.vcntq - // don't have to use pf ready signals - // if cmdq is not a load or store - ctrl.io.vec_iface.vcmdq_ready := vu.io.vec_cmdq.ready - ctrl.io.vec_iface.vximm1q_ready := vu.io.vec_ximm1q.ready - ctrl.io.vec_iface.vximm2q_ready := vu.io.vec_ximm2q.ready - ctrl.io.vec_iface.vcntq_ready := vu.io.vec_cntq.ready - ctrl.io.vec_iface.vpfcmdq_ready := vu.io.vec_pfcmdq.ready - ctrl.io.vec_iface.vpfximm1q_ready := vu.io.vec_pfximm1q.ready - ctrl.io.vec_iface.vpfximm2q_ready := vu.io.vec_pfximm2q.ready - ctrl.io.vec_iface.vpfcntq_ready := vu.io.vec_pfcntq.ready + ctrl.io.vec_iface.vpfcmdq <> vu.io.vpfcmdq + ctrl.io.vec_iface.vpfximm1q <> vu.io.vpfximm1q + ctrl.io.vec_iface.vpfximm2q <> vu.io.vpfximm2q + ctrl.io.vec_iface.vpfcntq <> vu.io.vpfcntq + + dpath.io.vec_iface.vpfcmdq <> vu.io.vpfcmdq + dpath.io.vec_iface.vpfximm1q <> vu.io.vpfximm1q + dpath.io.vec_iface.vpfximm2q <> vu.io.vpfximm2q + dpath.io.vec_iface.vpfcntq <> vu.io.vpfcntq // user level vector command queue ready signals - ctrl.io.vec_iface.vcmdq_user_ready := vu.io.vec_cmdq_user_ready - ctrl.io.vec_iface.vximm1q_user_ready := vu.io.vec_ximm1q_user_ready - ctrl.io.vec_iface.vximm2q_user_ready := vu.io.vec_ximm2q_user_ready + ctrl.io.vec_iface.vcmdq_user_ready := vu.io.vcmdq_user_ready + ctrl.io.vec_iface.vximm1q_user_ready := vu.io.vximm1q_user_ready + ctrl.io.vec_iface.vximm2q_user_ready := vu.io.vximm2q_user_ready // fences - ctrl.io.vec_iface.vfence_ready := vu.io.vec_fence_ready + ctrl.io.vec_iface.vfence_ready := vu.io.vfence_ready // irqs ctrl.io.vec_iface.irq := vu.io.irq diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala index 46afcc98..daa8e004 100644 --- a/rocket/src/main/scala/ctrl.scala +++ b/rocket/src/main/scala/ctrl.scala @@ -437,14 +437,14 @@ class Control(implicit conf: RocketConfiguration) extends Component vec_dec.io.inst := io.dpath.inst val s = io.dpath.status(SR_S) - val mask_cmdq_ready = !vec_dec.io.sigs.enq_cmdq || s && io.vec_iface.vcmdq_ready || !s && io.vec_iface.vcmdq_user_ready - val mask_ximm1q_ready = !vec_dec.io.sigs.enq_ximm1q || s && io.vec_iface.vximm1q_ready || !s && io.vec_iface.vximm1q_user_ready - val mask_ximm2q_ready = !vec_dec.io.sigs.enq_ximm2q || s && io.vec_iface.vximm2q_ready || !s && io.vec_iface.vximm2q_user_ready - val mask_cntq_ready = !vec_dec.io.sigs.enq_cntq || io.vec_iface.vcntq_ready - val mask_pfcmdq_ready = !vec_dec.io.sigs.enq_pfcmdq || io.vec_iface.vpfcmdq_ready - val mask_pfximm1q_ready = !vec_dec.io.sigs.enq_pfximm1q || io.vec_iface.vpfximm1q_ready - val mask_pfximm2q_ready = !vec_dec.io.sigs.enq_pfximm2q || io.vec_iface.vpfximm2q_ready - val mask_pfcntq_ready = !vec_dec.io.sigs.enq_pfcntq || io.vec_iface.vpfcntq_ready + val mask_cmdq_ready = !vec_dec.io.sigs.enq_cmdq || s && io.vec_iface.vcmdq.ready || !s && io.vec_iface.vcmdq_user_ready + val mask_ximm1q_ready = !vec_dec.io.sigs.enq_ximm1q || s && io.vec_iface.vximm1q.ready || !s && io.vec_iface.vximm1q_user_ready + val mask_ximm2q_ready = !vec_dec.io.sigs.enq_ximm2q || s && io.vec_iface.vximm2q.ready || !s && io.vec_iface.vximm2q_user_ready + val mask_cntq_ready = !vec_dec.io.sigs.enq_cntq || io.vec_iface.vcntq.ready + val mask_pfcmdq_ready = !vec_dec.io.sigs.enq_pfcmdq || io.vec_iface.vpfcmdq.ready + val mask_pfximm1q_ready = !vec_dec.io.sigs.enq_pfximm1q || io.vec_iface.vpfximm1q.ready + val mask_pfximm2q_ready = !vec_dec.io.sigs.enq_pfximm2q || io.vec_iface.vpfximm2q.ready + val mask_pfcntq_ready = !vec_dec.io.sigs.enq_pfcntq || io.vec_iface.vpfcntq.ready vec_stalld = id_vec_val && ( diff --git a/rocket/src/main/scala/ctrl_vec.scala b/rocket/src/main/scala/ctrl_vec.scala index 4fe89d5d..fd45b56b 100644 --- a/rocket/src/main/scala/ctrl_vec.scala +++ b/rocket/src/main/scala/ctrl_vec.scala @@ -4,6 +4,7 @@ import Chisel._ import Node._ import Constants._ import Instructions._ +import hwacha.Constants._ class ioCtrlDpathVec extends Bundle { @@ -19,23 +20,15 @@ class ioCtrlDpathVec extends Bundle class ioCtrlVecInterface extends Bundle { - val vcmdq_valid = Bool(OUTPUT) - val vcmdq_ready = Bool(INPUT) - val vximm1q_valid = Bool(OUTPUT) - val vximm1q_ready = Bool(INPUT) - val vximm2q_valid = Bool(OUTPUT) - val vximm2q_ready = Bool(INPUT) - val vcntq_valid = Bool(OUTPUT) - val vcntq_ready = Bool(INPUT) + val vcmdq = new FIFOIO()(Bits(width = SZ_VCMD)) + val vximm1q = new FIFOIO()(Bits(width = SZ_VIMM)) + val vximm2q = new FIFOIO()(Bits(width = SZ_VSTRIDE)) + val vcntq = new FIFOIO()(Bits(width = SZ_VLEN+1)) - val vpfcmdq_valid = Bool(OUTPUT) - val vpfcmdq_ready = Bool(INPUT) - val vpfximm1q_valid = Bool(OUTPUT) - val vpfximm1q_ready = Bool(INPUT) - val vpfximm2q_valid = Bool(OUTPUT) - val vpfximm2q_ready = Bool(INPUT) - val vpfcntq_valid = Bool(OUTPUT) - val vpfcntq_ready = Bool(INPUT) + val vpfcmdq = new FIFOIO()(Bits(width = SZ_VCMD)) + val vpfximm1q = new FIFOIO()(Bits(width = SZ_VIMM)) + val vpfximm2q = new FIFOIO()(Bits(width = SZ_VSTRIDE)) + val vpfcntq = new FIFOIO()(Bits(width = SZ_VLEN)) val vcmdq_user_ready = Bool(INPUT) val vximm1q_user_ready = Bool(INPUT) @@ -207,14 +200,14 @@ class rocketCtrlVec extends Component val enq_pfximm2q_mask_pfq = dec.io.sigs.enq_pfximm2q && (!dec.io.sigs.pfaq || io.dpath.pfq) val enq_pfcntq_mask_pfq = dec.io.sigs.enq_pfcntq && (!dec.io.sigs.pfaq || io.dpath.pfq) - val mask_cmdq_ready = !dec.io.sigs.enq_cmdq || io.s && io.iface.vcmdq_ready || !io.s && io.iface.vcmdq_user_ready - val mask_ximm1q_ready = !dec.io.sigs.enq_ximm1q || io.s && io.iface.vximm1q_ready || !io.s && io.iface.vximm1q_user_ready - val mask_ximm2q_ready = !dec.io.sigs.enq_ximm2q || io.s && io.iface.vximm2q_ready || !io.s && io.iface.vximm2q_user_ready - val mask_cntq_ready = !dec.io.sigs.enq_cntq || io.iface.vcntq_ready - val mask_pfcmdq_ready = !enq_pfcmdq_mask_pfq || io.iface.vpfcmdq_ready - val mask_pfximm1q_ready = !enq_pfximm1q_mask_pfq || io.iface.vpfximm1q_ready - val mask_pfximm2q_ready = !enq_pfximm2q_mask_pfq || io.iface.vpfximm2q_ready - val mask_pfcntq_ready = !enq_pfcntq_mask_pfq || io.iface.vpfcntq_ready + val mask_cmdq_ready = !dec.io.sigs.enq_cmdq || io.s && io.iface.vcmdq.ready || !io.s && io.iface.vcmdq_user_ready + val mask_ximm1q_ready = !dec.io.sigs.enq_ximm1q || io.s && io.iface.vximm1q.ready || !io.s && io.iface.vximm1q_user_ready + val mask_ximm2q_ready = !dec.io.sigs.enq_ximm2q || io.s && io.iface.vximm2q.ready || !io.s && io.iface.vximm2q_user_ready + val mask_cntq_ready = !dec.io.sigs.enq_cntq || io.iface.vcntq.ready + val mask_pfcmdq_ready = !enq_pfcmdq_mask_pfq || io.iface.vpfcmdq.ready + val mask_pfximm1q_ready = !enq_pfximm1q_mask_pfq || io.iface.vpfximm1q.ready + val mask_pfximm2q_ready = !enq_pfximm2q_mask_pfq || io.iface.vpfximm2q.ready + val mask_pfcntq_ready = !enq_pfcntq_mask_pfq || io.iface.vpfcntq.ready io.dpath.wen := dec.io.sigs.wen io.dpath.fn := dec.io.sigs.fn @@ -222,42 +215,42 @@ class rocketCtrlVec extends Component io.dpath.sel_vimm := dec.io.sigs.sel_vimm io.dpath.sel_vimm2 := dec.io.sigs.sel_vimm2 - io.iface.vcmdq_valid := + io.iface.vcmdq.valid := valid_common && dec.io.sigs.enq_cmdq && mask_ximm1q_ready && mask_ximm2q_ready && mask_cntq_ready && mask_pfcmdq_ready && mask_pfximm1q_ready && mask_pfximm2q_ready && mask_pfcntq_ready - io.iface.vximm1q_valid := + io.iface.vximm1q.valid := valid_common && mask_cmdq_ready && dec.io.sigs.enq_ximm1q && mask_ximm2q_ready && mask_cntq_ready && mask_pfcmdq_ready && mask_pfximm1q_ready && mask_pfximm2q_ready && mask_pfcntq_ready - io.iface.vximm2q_valid := + io.iface.vximm2q.valid := valid_common && mask_cmdq_ready && mask_ximm1q_ready && dec.io.sigs.enq_ximm2q && mask_cntq_ready && mask_pfcmdq_ready && mask_pfximm1q_ready && mask_pfximm2q_ready && mask_pfcntq_ready - io.iface.vcntq_valid := + io.iface.vcntq.valid := valid_common && mask_cmdq_ready && mask_ximm1q_ready && mask_ximm2q_ready && dec.io.sigs.enq_cntq && mask_pfcmdq_ready && mask_pfximm1q_ready && mask_pfximm2q_ready && mask_pfcntq_ready - io.iface.vpfcmdq_valid := + io.iface.vpfcmdq.valid := valid_common && mask_cmdq_ready && mask_ximm1q_ready && mask_ximm2q_ready && mask_cntq_ready && enq_pfcmdq_mask_pfq && mask_pfximm1q_ready && mask_pfximm2q_ready && mask_pfcntq_ready - io.iface.vpfximm1q_valid := + io.iface.vpfximm1q.valid := valid_common && mask_cmdq_ready && mask_ximm1q_ready && mask_ximm2q_ready && mask_cntq_ready && mask_pfcmdq_ready && enq_pfximm1q_mask_pfq && mask_pfximm2q_ready && mask_pfcntq_ready - io.iface.vpfximm2q_valid := + io.iface.vpfximm2q.valid := valid_common && mask_cmdq_ready && mask_ximm1q_ready && mask_ximm2q_ready && mask_cntq_ready && mask_pfcmdq_ready && mask_pfximm1q_ready && enq_pfximm2q_mask_pfq && mask_pfcntq_ready - io.iface.vpfcntq_valid := + io.iface.vpfcntq.valid := valid_common && mask_cmdq_ready && mask_ximm1q_ready && mask_ximm2q_ready && mask_cntq_ready && mask_pfcmdq_ready && mask_pfximm1q_ready && mask_pfximm2q_ready && enq_pfcntq_mask_pfq diff --git a/rocket/src/main/scala/dpath_vec.scala b/rocket/src/main/scala/dpath_vec.scala index 8a4faabb..6bf6a8b1 100644 --- a/rocket/src/main/scala/dpath_vec.scala +++ b/rocket/src/main/scala/dpath_vec.scala @@ -8,11 +8,16 @@ import hwacha.Constants._ class ioDpathVecInterface extends Bundle { - val vcmdq_bits = Bits(OUTPUT, SZ_VCMD) - val vximm1q_bits = Bits(OUTPUT, SZ_VIMM) - val vximm2q_bits = Bits(OUTPUT, SZ_VSTRIDE) - val vcntq_bits = Bits(OUTPUT, SZ_VLEN) - val vcntq_last = Bool(OUTPUT) + val vcmdq = new FIFOIO()(Bits(width = SZ_VCMD)) + val vximm1q = new FIFOIO()(Bits(width = SZ_VIMM)) + val vximm2q = new FIFOIO()(Bits(width = SZ_VSTRIDE)) + val vcntq = new FIFOIO()(Bits(width = SZ_VLEN+1)) + + val vpfcmdq = new FIFOIO()(Bits(width = SZ_VCMD)) + val vpfximm1q = new FIFOIO()(Bits(width = SZ_VIMM)) + val vpfximm2q = new FIFOIO()(Bits(width = SZ_VSTRIDE)) + val vpfcntq = new FIFOIO()(Bits(width = SZ_VLEN)) + val evac_addr = Bits(OUTPUT, 64) val irq_aux = Bits(INPUT, 64) } @@ -147,7 +152,7 @@ class rocketDpathVec extends Component val appvlm1 = appvl - UFix(1) - io.iface.vcmdq_bits := + io.iface.vcmdq.bits := Mux(io.ctrl.sel_vcmd === VCMD_I, Cat(Bits(0,2), Bits(0,4), io.inst(9,8), Bits(0,6), Bits(0,6)), Mux(io.ctrl.sel_vcmd === VCMD_F, Cat(Bits(0,2), Bits(1,3), io.inst(9,7), Bits(0,6), Bits(0,6)), Mux(io.ctrl.sel_vcmd === VCMD_TX, Cat(Bits(1,2), io.inst(13,8), Bits(0,1), io.waddr, Bits(0,1), io.raddr1), @@ -157,16 +162,21 @@ class rocketDpathVec extends Component Mux(io.ctrl.sel_vcmd === VCMD_A, io.wdata(SZ_VCMD-1, 0), Bits(0,20)))))))) - io.iface.vximm1q_bits := + io.iface.vximm1q.bits := Mux(io.ctrl.sel_vimm === VIMM_VLEN, Cat(Bits(0,29), io.vecbankcnt, io.vecbank, nfregs(5,0), nxregs(5,0), appvlm1(10,0)), io.wdata) // VIMM_ALU - io.iface.vximm2q_bits := + io.iface.vximm2q.bits := Mux(io.ctrl.sel_vimm2 === VIMM2_RS2, io.rs2, io.wdata) // VIMM2_ALU - io.iface.vcntq_bits := io.wdata(SZ_VLEN-1, 0) - io.iface.vcntq_last := io.rs2(1) + val last = io.rs2(1) + io.iface.vcntq.bits := Cat(last, io.iface.vpfcntq.bits) + + io.iface.vpfcmdq.bits := io.iface.vcmdq.bits + io.iface.vpfximm1q.bits := io.iface.vximm1q.bits + io.iface.vpfximm2q.bits := io.iface.vximm2q.bits + io.iface.vpfcntq.bits := io.wdata(SZ_VLEN-1, 0) io.iface.evac_addr := io.wdata