riscv/rocket-chip
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Update PTE format to reflect reserved bits

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Andrew Waterman 2015-04-04 15:19:15 -07:00
parent d912ea265e
commit bce62d5774
1 changed files with 2 additions and 1 deletions
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rocket/src/main/scala/ptw.scala
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@ -33,7 +33,8 @@ class DatapathPTWIO extends CoreBundle {
class PTE extends CoreBundle { class PTE extends CoreBundle {
val ppn = Bits(width = ppnBits) val ppn = Bits(width = ppnBits)
val reserved = Bits(width = 2) val reserved = Bits(width = 16)
val reserved_for_software = Bits(width = 2)
val d = Bool() val d = Bool()
val r = Bool() val r = Bool()
val g = Bool() val g = Bool()