diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 11ac09ce..bdbde9cd 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -171,6 +171,8 @@ class Uncore(implicit val p: Parameters) extends Module
   scrArb.io.in(0) <> htif.io.scr
   scrArb.io.in(1) <> outmemsys.io.scr
   scrFile.io.smi <> scrArb.io.out
+  scrFile.io.scr.attach(UInt(nTiles), "N_CORES", false, true)
+  scrFile.io.scr.attach(UInt(p(MMIOBase) >> 20), "MMIO_BASE", false, true)
   // scrFile.io.scr <> (... your SCR connections ...)
 
   // Configures the enabled memory channels.  This can't be changed while the
diff --git a/uncore b/uncore
index 42549fd7..01e9a7f0 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit 42549fd7cfa86075a82cbbd10adf6d41b3dcad67
+Subproject commit 01e9a7f0ff0c36ac075d4329b138c2fc998ad627