riscv/rocket-chip
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Merge remote-tracking branch 'origin/master' into rocc-fpu-port

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Yunsup Lee 2015-04-29 00:43:53 -07:00
commit b9fb1bb46e
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/nbdcache.scala
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@ -511,7 +511,7 @@ class ProbeUnit extends L1HellaCacheModule {
req := io.req.bits req := io.req.bits
} }
val reply = old_coh.makeRelease(req, req.client_xact_id) val reply = old_coh.makeRelease(req)
io.req.ready := state === s_invalid io.req.ready := state === s_invalid
io.rep.valid := state === s_release && io.rep.valid := state === s_release &&
!(tag_matches && old_coh.requiresVoluntaryWriteback()) // Otherwise WBU will issue release !(tag_matches && old_coh.requiresVoluntaryWriteback()) // Otherwise WBU will issue release