diplomacy: API beautification
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@ -82,7 +82,7 @@ class BusBlocker(params: BusBlockerParams)(implicit p: Parameters) extends TLBus
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lazy val module = new LazyModuleImp(this) {
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// We need to be able to represent +1 larger than the largest populated address
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val addressBits = log2Ceil(nodeOut.out(0)._2.manager.maxAddress+1+1)
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val addressBits = log2Ceil(nodeOut.edges.out(0).manager.maxAddress+1+1)
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val pmps = RegInit(Vec.fill(params.pmpRegisters) { DevicePMP(addressBits, params.pageBits) })
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val blocks = pmps.tail.map(_.blockPriorAddress) :+ Bool(false)
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controlNode.regmap(0 -> (pmps zip blocks).map { case (p, b) => p.fields(b) }.toList.flatten)
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@ -68,7 +68,8 @@ class CoreplexLocalInterrupter(params: ClintParams)(implicit p: Parameters) exte
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val timecmp = Seq.fill(nTiles) { Seq.fill(timeWidth/regWidth)(Reg(UInt(width = regWidth))) }
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val ipi = Seq.fill(nTiles) { RegInit(UInt(0, width = 1)) }
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intnode.in.map(_._1).zipWithIndex.foreach { case (int, i) =>
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val (intnode_in, _) = intnode.in.unzip
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intnode_in.zipWithIndex.foreach { case (int, i) =>
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int(0) := ShiftRegister(ipi(i)(0), params.intStages) // msip
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int(1) := ShiftRegister(time.asUInt >= timecmp(i).asUInt, params.intStages) // mtip
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}
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@ -91,12 +91,12 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
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sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) })
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/* Negotiated sizes */
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def nDevices: Int = intnode.in.map(_._2.source.num).sum
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def nDevices: Int = intnode.edges.in.map(_.source.num).sum
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def nPriorities = min(params.maxPriorities, nDevices)
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def nHarts = intnode.out.map(_._2.source.num).sum
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def nHarts = intnode.edges.out.map(_.source.num).sum
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// Assign all the devices unique ranges
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lazy val sources = intnode.in.map(_._2.source)
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lazy val sources = intnode.edges.in.map(_.source)
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lazy val flatSources = (sources zip sources.map(_.num).scanLeft(0)(_+_).init).map {
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case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o)))
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}.flatten
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