From b9a2e4c243bd487aff1161c6465c9e7b0e405949 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 15 Sep 2017 14:44:07 -0700 Subject: [PATCH] diplomacy: API beautification --- src/main/scala/coreplex/Ports.scala | 12 ++++++------ src/main/scala/coreplex/SystemBus.scala | 2 +- src/main/scala/devices/debug/Debug.scala | 6 +++--- src/main/scala/devices/tilelink/BusBlocker.scala | 2 +- src/main/scala/devices/tilelink/Clint.scala | 3 ++- src/main/scala/devices/tilelink/Plic.scala | 6 +++--- src/main/scala/diplomacy/Nodes.scala | 4 +++- src/main/scala/rocket/Frontend.scala | 2 +- src/main/scala/rocket/HellaCache.scala | 4 ++-- src/main/scala/rocket/ICache.scala | 2 ++ src/main/scala/rocket/PTW.scala | 2 +- src/main/scala/rocket/ScratchpadSlavePort.scala | 2 +- src/main/scala/tile/Interrupts.scala | 3 ++- src/main/scala/tile/RocketTile.scala | 4 ++-- src/main/scala/tilelink/NodeNumberer.scala | 2 +- src/main/scala/tilelink/RegisterRouter.scala | 2 ++ src/main/scala/util/HeterogeneousBag.scala | 5 +++++ 17 files changed, 38 insertions(+), 25 deletions(-) diff --git a/src/main/scala/coreplex/Ports.scala b/src/main/scala/coreplex/Ports.scala index 4eb975ab..a526561c 100644 --- a/src/main/scala/coreplex/Ports.scala +++ b/src/main/scala/coreplex/Ports.scala @@ -79,7 +79,7 @@ trait HasMasterAXI4MemPortBundle { /** Actually generates the corresponding IO in the concrete Module */ trait HasMasterAXI4MemPortModuleImp extends LazyModuleImp with HasMasterAXI4MemPortBundle { val outer: HasMasterAXI4MemPort - val mem_axi4 = IO(HeterogeneousBag(outer.mem_axi4.in.map(_._1.cloneType))) + val mem_axi4 = IO(HeterogeneousBag.fromNode(outer.mem_axi4.in)) (mem_axi4 zip outer.mem_axi4.in) foreach { case (i, (o, _)) => i <> o } val nMemoryChannels = outer.nMemoryChannels } @@ -119,7 +119,7 @@ trait HasMasterAXI4MMIOPortBundle { /** Actually generates the corresponding IO in the concrete Module */ trait HasMasterAXI4MMIOPortModuleImp extends LazyModuleImp with HasMasterAXI4MMIOPortBundle { val outer: HasMasterAXI4MMIOPort - val mmio_axi4 = IO(HeterogeneousBag(outer.mmio_axi4.in.map(_._1.cloneType))) + val mmio_axi4 = IO(HeterogeneousBag.fromNode(outer.mmio_axi4.in)) (mmio_axi4 zip outer.mmio_axi4.in) foreach { case (i, (o, _)) => i <> o } } @@ -159,7 +159,7 @@ trait HasSlaveAXI4PortBundle { /** Actually generates the corresponding IO in the concrete Module */ trait HasSlaveAXI4PortModuleImp extends LazyModuleImp with HasSlaveAXI4PortBundle { val outer: HasSlaveAXI4Port - val l2_frontend_bus_axi4 = IO(HeterogeneousBag(outer.l2FrontendAXI4Node.out.map(_._1.cloneType)).flip) + val l2_frontend_bus_axi4 = IO(HeterogeneousBag.fromNode(outer.l2FrontendAXI4Node.out).flip) (outer.l2FrontendAXI4Node.out zip l2_frontend_bus_axi4) foreach { case ((i, _), o) => i <> o } } @@ -201,7 +201,7 @@ trait HasMasterTLMMIOPortBundle { /** Actually generates the corresponding IO in the concrete Module */ trait HasMasterTLMMIOPortModuleImp extends LazyModuleImp with HasMasterTLMMIOPortBundle { val outer: HasMasterTLMMIOPort - val mmio_tl = IO(HeterogeneousBag(outer.mmio_tl.in.map(_._1.cloneType))) + val mmio_tl = IO(HeterogeneousBag.fromNode(outer.mmio_tl.in)) (mmio_tl zip outer.mmio_tl.out) foreach { case (i, (o, _)) => i <> o } } @@ -239,7 +239,7 @@ trait HasSlaveTLPortBundle { /** Actually generates the corresponding IO in the concrete Module */ trait HasSlaveTLPortModuleImp extends LazyModuleImp with HasSlaveTLPortBundle { val outer: HasSlaveTLPort - val l2_frontend_bus_tl = IO(HeterogeneousBag(outer.l2FrontendTLNode.out.map(_._1.cloneType)).flip) + val l2_frontend_bus_tl = IO(HeterogeneousBag.fromNode(outer.l2FrontendTLNode.out).flip) (outer.l2FrontendTLNode.in zip l2_frontend_bus_tl) foreach { case ((i, _), o) => i <> o } } @@ -264,7 +264,7 @@ class SimAXIMem(channels: Int, forceSize: BigInt = 0)(implicit p: Parameters) ex lazy val module = new LazyModuleImp(this) { val io = IO(new Bundle { - val axi4 = HeterogeneousBag(node.out.map(_._1.cloneType)).flip + val axi4 = HeterogeneousBag.fromNode(node.out).flip }) (node.out zip io.axi4) foreach { case ((i, _), o) => i <> o } } diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala index 98f0c5ba..384da306 100644 --- a/src/main/scala/coreplex/SystemBus.scala +++ b/src/main/scala/coreplex/SystemBus.scala @@ -22,7 +22,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr private val master_splitter = LazyModule(new TLSplitter) // Allows cycle-free connection to external networks master_splitter.suggestName(s"${busName}_master_TLSplitter") inwardNode :=* master_splitter.node - def busView = master_splitter.node.in.head._2 + def busView = master_splitter.node.edges.in.head protected def inwardSplitNode: TLInwardNode = master_splitter.node protected def outwardSplitNode: TLOutwardNode = master_splitter.node diff --git a/src/main/scala/devices/debug/Debug.scala b/src/main/scala/devices/debug/Debug.scala index 8d26d50b..60577171 100644 --- a/src/main/scala/devices/debug/Debug.scala +++ b/src/main/scala/devices/debug/Debug.scala @@ -353,8 +353,9 @@ class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyMod debugIntNxt := debugIntRegs + val (intnode_out, _) = intnode.out.unzip for (component <- 0 until nComponents) { - intnode.out(component)._1(0) := debugIntRegs(component) + intnode_out(component)(0) := debugIntRegs(component) } // Halt request registers are set & cleared by writes to DMCONTROL.haltreq @@ -1015,7 +1016,6 @@ class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int)(implici lazy val module = new LazyModuleImp(this) { val io = IO(new Bundle { - // this comes from tlClk domain. // These are all asynchronous and come from Outer val dmactive = Bool(INPUT) val innerCtrl = new AsyncBundle(1, new DebugInternalBundle()).flip @@ -1045,7 +1045,7 @@ class TLDebugModule(implicit p: Parameters) extends LazyModule { val intnode = IntIdentityNode() val dmOuter = LazyModule(new TLDebugModuleOuterAsync(device)(p)) - val dmInner = LazyModule(new TLDebugModuleInnerAsync(device, () => {intnode.edges._2.size})(p)) + val dmInner = LazyModule(new TLDebugModuleInnerAsync(device, () => {intnode.edges.out.size})(p)) dmInner.dmiNode := dmOuter.dmiInnerNode dmInner.tlNode := node diff --git a/src/main/scala/devices/tilelink/BusBlocker.scala b/src/main/scala/devices/tilelink/BusBlocker.scala index 7d5f476f..b057ab8d 100644 --- a/src/main/scala/devices/tilelink/BusBlocker.scala +++ b/src/main/scala/devices/tilelink/BusBlocker.scala @@ -82,7 +82,7 @@ class BusBlocker(params: BusBlockerParams)(implicit p: Parameters) extends TLBus lazy val module = new LazyModuleImp(this) { // We need to be able to represent +1 larger than the largest populated address - val addressBits = log2Ceil(nodeOut.out(0)._2.manager.maxAddress+1+1) + val addressBits = log2Ceil(nodeOut.edges.out(0).manager.maxAddress+1+1) val pmps = RegInit(Vec.fill(params.pmpRegisters) { DevicePMP(addressBits, params.pageBits) }) val blocks = pmps.tail.map(_.blockPriorAddress) :+ Bool(false) controlNode.regmap(0 -> (pmps zip blocks).map { case (p, b) => p.fields(b) }.toList.flatten) diff --git a/src/main/scala/devices/tilelink/Clint.scala b/src/main/scala/devices/tilelink/Clint.scala index 1cd759a5..1419c137 100644 --- a/src/main/scala/devices/tilelink/Clint.scala +++ b/src/main/scala/devices/tilelink/Clint.scala @@ -68,7 +68,8 @@ class CoreplexLocalInterrupter(params: ClintParams)(implicit p: Parameters) exte val timecmp = Seq.fill(nTiles) { Seq.fill(timeWidth/regWidth)(Reg(UInt(width = regWidth))) } val ipi = Seq.fill(nTiles) { RegInit(UInt(0, width = 1)) } - intnode.in.map(_._1).zipWithIndex.foreach { case (int, i) => + val (intnode_in, _) = intnode.in.unzip + intnode_in.zipWithIndex.foreach { case (int, i) => int(0) := ShiftRegister(ipi(i)(0), params.intStages) // msip int(1) := ShiftRegister(time.asUInt >= timecmp(i).asUInt, params.intStages) // mtip } diff --git a/src/main/scala/devices/tilelink/Plic.scala b/src/main/scala/devices/tilelink/Plic.scala index a0ee455a..73c9d681 100644 --- a/src/main/scala/devices/tilelink/Plic.scala +++ b/src/main/scala/devices/tilelink/Plic.scala @@ -91,12 +91,12 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }) /* Negotiated sizes */ - def nDevices: Int = intnode.in.map(_._2.source.num).sum + def nDevices: Int = intnode.edges.in.map(_.source.num).sum def nPriorities = min(params.maxPriorities, nDevices) - def nHarts = intnode.out.map(_._2.source.num).sum + def nHarts = intnode.edges.out.map(_.source.num).sum // Assign all the devices unique ranges - lazy val sources = intnode.in.map(_._2.source) + lazy val sources = intnode.edges.in.map(_.source) lazy val flatSources = (sources zip sources.map(_.num).scanLeft(0)(_+_).init).map { case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o))) }.flatten diff --git a/src/main/scala/diplomacy/Nodes.scala b/src/main/scala/diplomacy/Nodes.scala index c129a183..98a80b50 100644 --- a/src/main/scala/diplomacy/Nodes.scala +++ b/src/main/scala/diplomacy/Nodes.scala @@ -96,6 +96,7 @@ object BaseNode protected[diplomacy] var serial = 0 } +// !!! rename the nodes we bind? case class NodeHandle[DI, UI, BI <: Data, DO, UO, BO <: Data] (inward: InwardNode[DI, UI, BI], outward: OutwardNode[DO, UO, BO]) extends Object with InwardNodeHandle[DI, UI, BI] with OutwardNodeHandle[DO, UO, BO] @@ -177,6 +178,7 @@ trait OutwardNode[DO, UO, BO <: Data] extends BaseNode with OutwardNodeHandle[DO protected[diplomacy] val oParams: Seq[DO] } +case class Edges[EI, EO](in: EI, out: EO) sealed abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( inner: InwardNodeImp [DI, UI, EI, BI], outer: OutwardNodeImp[DO, UO, EO, BO])( @@ -243,7 +245,7 @@ sealed abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( protected[diplomacy] lazy val edgesIn = (iPorts zip iParams).map { case ((o, n, p), i) => inner.edgeI(n.oParams(o), i, p) } // If you need access to the edges of a foreign Node, use this method (in/out create bundles) - lazy val edges = (edgesIn, edgesOut) + lazy val edges = Edges(edgesIn, edgesOut) protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map(e => Wire(outer.bundleO(e))) protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn .map(e => Wire(inner.bundleI(e))) diff --git a/src/main/scala/rocket/Frontend.scala b/src/main/scala/rocket/Frontend.scala index 948e9676..ee224f53 100644 --- a/src/main/scala/rocket/Frontend.scala +++ b/src/main/scala/rocket/Frontend.scala @@ -75,7 +75,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer) with HasCoreParameters with HasL1ICacheParameters { val io = IO(new FrontendBundle(outer)) - implicit val edge = outer.masterNode.out(0)._2 + implicit val edge = outer.masterNode.edges.out(0) val icache = outer.icache.module require(fetchWidth*coreInstBytes == outer.icacheParams.fetchBytes) diff --git a/src/main/scala/rocket/HellaCache.scala b/src/main/scala/rocket/HellaCache.scala index 3463758c..558e0259 100644 --- a/src/main/scala/rocket/HellaCache.scala +++ b/src/main/scala/rocket/HellaCache.scala @@ -181,8 +181,8 @@ class HellaCacheBundle(outer: HellaCache)(implicit p: Parameters) extends CoreBu class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer) with HasL1HellaCacheParameters { - implicit val edge = outer.node.out(0)._2 - val tl_out = outer.node.out(0)._1 + implicit val edge = outer.node.edges.out(0) + val (tl_out, _) = outer.node.out(0) val io = IO(new HellaCacheBundle(outer)) private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allUncacheable) diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala index cf0a6b4d..c7c2fabb 100644 --- a/src/main/scala/rocket/ICache.scala +++ b/src/main/scala/rocket/ICache.scala @@ -109,6 +109,8 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) val io = IO(new ICacheBundle(outer)) val (tl_out, edge_out) = outer.masterNode.out(0) + // Option.unzip does not exist :-( + // val (tl_in, edge_in) = outer.slaveNode.map(_.in(0)).unzip val tl_in = outer.slaveNode.map(_.in(0)._1) val edge_in = outer.slaveNode.map(_.in(0)._2) diff --git a/src/main/scala/rocket/PTW.scala b/src/main/scala/rocket/PTW.scala index 1cab0d93..4618715f 100644 --- a/src/main/scala/rocket/PTW.scala +++ b/src/main/scala/rocket/PTW.scala @@ -283,7 +283,7 @@ trait CanHavePTW extends HasHellaCache { trait CanHavePTWModule extends HasHellaCacheModule { val outer: CanHavePTW val ptwPorts = ListBuffer(outer.dcache.module.io.ptw) - val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.out(0)._2, outer.p)) + val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p)) if (outer.usingPTW) dcachePorts += ptw.io.mem } diff --git a/src/main/scala/rocket/ScratchpadSlavePort.scala b/src/main/scala/rocket/ScratchpadSlavePort.scala index 45a0f952..5f769962 100644 --- a/src/main/scala/rocket/ScratchpadSlavePort.scala +++ b/src/main/scala/rocket/ScratchpadSlavePort.scala @@ -127,7 +127,7 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend { } def findScratchpadFromICache: Option[AddressSet] = scratch.map { s => - val finalNode = frontend.masterNode.out.head._2.manager.managers.find(_.nodePath.last == s.node) + val finalNode = frontend.masterNode.edges.out.head.manager.managers.find(_.nodePath.last == s.node) require (finalNode.isDefined, "Could not find the scratch pad; not reachable via icache?") require (finalNode.get.address.size == 1, "Scratchpad address space was fragmented!") finalNode.get.address(0) diff --git a/src/main/scala/tile/Interrupts.scala b/src/main/scala/tile/Interrupts.scala index 4df8564e..dcccada3 100644 --- a/src/main/scala/tile/Interrupts.scala +++ b/src/main/scala/tile/Interrupts.scala @@ -56,6 +56,7 @@ trait HasExternalInterruptsModule { val core_ips = core.lip - (async_ips ++ periph_ips ++ seip ++ core_ips).zip(outer.intNode.in(0)._1).foreach { case(c, i) => c := i } + val (interrupts, _) = outer.intNode.in(0) + (async_ips ++ periph_ips ++ seip ++ core_ips).zip(interrupts).foreach { case(c, i) => c := i } } } diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala index 1b42a963..710ce335 100644 --- a/src/main/scala/tile/RocketTile.scala +++ b/src/main/scala/tile/RocketTile.scala @@ -82,7 +82,7 @@ class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p })) // Find all the caches - val outer = masterNode.out.map(_._2) + val outer = masterNode.edges.out .flatMap(_.manager.managers) .filter(_.supportsAcquireB) .flatMap(_.resources.headOption) @@ -115,7 +115,7 @@ class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p Resource(cpuDevice, "reg").bind(ResourceInt(BigInt(hartid))) Resource(intcDevice, "reg").bind(ResourceInt(BigInt(hartid))) - intNode.in.flatMap(_._2.source.sources).map { case s => + intNode.edges.in.flatMap(_.source.sources).map { case s => for (i <- s.range.start until s.range.end) { csrIntMap.lift(i).foreach { j => s.resources.foreach { r => diff --git a/src/main/scala/tilelink/NodeNumberer.scala b/src/main/scala/tilelink/NodeNumberer.scala index 6c3d17be..eb5c0a9b 100644 --- a/src/main/scala/tilelink/NodeNumberer.scala +++ b/src/main/scala/tilelink/NodeNumberer.scala @@ -43,7 +43,7 @@ class TLNodeNumberer(nodeAddressOffset: Option[Int] = None)(implicit p: Paramete val node = TLNodeNumbererNode(nodeAddressOffset) lazy val module = new LazyModuleImp(this) { - val minNodeOffset = log2Ceil(node.out.map(_._2.manager.maxAddress).max) + val minNodeOffset = log2Ceil(node.edges.out.map(_.manager.maxAddress).max) val nodeOffset = nodeAddressOffset.getOrElse(minNodeOffset) (node.in zip node.out).zipWithIndex foreach { case (((in, _), (out, _)), i) => diff --git a/src/main/scala/tilelink/RegisterRouter.scala b/src/main/scala/tilelink/RegisterRouter.scala index 403f8da7..bf523af7 100644 --- a/src/main/scala/tilelink/RegisterRouter.scala +++ b/src/main/scala/tilelink/RegisterRouter.scala @@ -129,3 +129,5 @@ class TLRegisterRouter[B <: TLRegBundleBase, M <: LazyModuleImp]( lazy val module = moduleBuilder(bundleBuilder(TLRegBundleArg()), this) } + +// !!! eliminate third trait diff --git a/src/main/scala/util/HeterogeneousBag.scala b/src/main/scala/util/HeterogeneousBag.scala index aec7e321..a48743ea 100644 --- a/src/main/scala/util/HeterogeneousBag.scala +++ b/src/main/scala/util/HeterogeneousBag.scala @@ -17,3 +17,8 @@ final case class HeterogeneousBag[T <: Data](elts: Seq[T]) extends Record with c override def hashCode: Int = super[Record].hashCode override def equals(that: Any): Boolean = super[Record].equals(that) } + +object HeterogeneousBag +{ + def fromNode[D <: Data, E](elts: Seq[(D, E)]) = new HeterogeneousBag(elts.map(_._1.cloneType)) +}