101 lines
3.0 KiB
Scala
101 lines
3.0 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.devices.tilelink
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.coreplex.HasPeripheryBus
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.regmapper._
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import freechips.rocketchip.tile.XLen
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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import scala.math.{min,max}
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object ClintConsts
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{
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def msipOffset(hart: Int) = hart * msipBytes
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def timecmpOffset(hart: Int) = 0x4000 + hart * timecmpBytes
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def timeOffset = 0xbff8
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def msipBytes = 4
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def timecmpBytes = 8
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def size = 0x10000
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def timeWidth = 64
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def regWidth = 32
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def ints = 2
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}
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case class ClintParams(baseAddress: BigInt = 0x02000000, intStages: Int = 0)
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{
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def address = AddressSet(baseAddress, ClintConsts.size-1)
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}
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case object ClintKey extends Field(ClintParams())
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class CoreplexLocalInterrupter(params: ClintParams)(implicit p: Parameters) extends LazyModule
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{
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import ClintConsts._
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// clint0 => at most 4095 devices
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val device = new SimpleDevice("clint", Seq("riscv,clint0")) {
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override val alwaysExtended = true
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}
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val node = TLRegisterNode(
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address = Seq(params.address),
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device = device,
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beatBytes = p(XLen)/8)
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val intnode = IntNexusNode(
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numSourcePorts = 0 to 1024,
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numSinkPorts = 0 to 0,
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sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(ints, Seq(Resource(device, "int"))))) },
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sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) })
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lazy val module = new LazyModuleImp(this) {
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val io = IO(new Bundle {
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val rtcTick = Bool(INPUT)
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})
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val time = Seq.fill(timeWidth/regWidth)(Reg(init=UInt(0, width = regWidth)))
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when (io.rtcTick) {
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val newTime = time.asUInt + UInt(1)
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for ((reg, i) <- time zip (0 until timeWidth by regWidth))
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reg := newTime >> i
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}
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val nTiles = intnode.out.size
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val timecmp = Seq.fill(nTiles) { Seq.fill(timeWidth/regWidth)(Reg(UInt(width = regWidth))) }
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val ipi = Seq.fill(nTiles) { RegInit(UInt(0, width = 1)) }
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val (intnode_in, _) = intnode.in.unzip
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intnode_in.zipWithIndex.foreach { case (int, i) =>
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int(0) := ShiftRegister(ipi(i)(0), params.intStages) // msip
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int(1) := ShiftRegister(time.asUInt >= timecmp(i).asUInt, params.intStages) // mtip
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}
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/* 0000 msip hart 0
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* 0004 msip hart 1
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* 4000 mtimecmp hart 0 lo
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* 4004 mtimecmp hart 0 hi
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* 4008 mtimecmp hart 1 lo
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* 400c mtimecmp hart 1 hi
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* bff8 mtime lo
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* bffc mtime hi
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*/
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def makeRegFields(s: Seq[UInt]) = s.map(r => RegField(regWidth, r))
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node.regmap(
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0 -> makeRegFields(ipi),
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timecmpOffset(0) -> makeRegFields(timecmp.flatten),
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timeOffset -> makeRegFields(time))
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}
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}
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/** Trait that will connect a Clint to a coreplex */
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trait HasPeripheryClint extends HasPeripheryBus {
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val clint = LazyModule(new CoreplexLocalInterrupter(p(ClintKey)))
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clint.node := pbus.toVariableWidthSlaves
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}
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