diplomacy: API beautification

src/main/scala/devices/debug/Debug.scala

@@ -353,8 +353,9 @@ class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyMod
 
     debugIntNxt := debugIntRegs
 
+    val (intnode_out, _) = intnode.out.unzip
     for (component <- 0 until nComponents) {
-      intnode.out(component)._1(0) := debugIntRegs(component)
+      intnode_out(component)(0) := debugIntRegs(component)
     }
 
     // Halt request registers are set & cleared by writes to DMCONTROL.haltreq
@@ -1015,7 +1016,6 @@ class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int)(implici
   lazy val module = new LazyModuleImp(this) {
 
     val io = IO(new Bundle {
-      // this comes from tlClk domain.
       // These are all asynchronous and come from Outer
       val dmactive = Bool(INPUT)
       val innerCtrl = new AsyncBundle(1, new DebugInternalBundle()).flip
@@ -1045,7 +1045,7 @@ class TLDebugModule(implicit p: Parameters) extends LazyModule {
   val intnode = IntIdentityNode()
 
   val dmOuter = LazyModule(new TLDebugModuleOuterAsync(device)(p))
-  val dmInner = LazyModule(new TLDebugModuleInnerAsync(device, () => {intnode.edges._2.size})(p))
+  val dmInner = LazyModule(new TLDebugModuleInnerAsync(device, () => {intnode.edges.out.size})(p))
 
   dmInner.dmiNode := dmOuter.dmiInnerNode
   dmInner.tlNode := node

src/main/scala/devices/tilelink/BusBlocker.scala

@@ -82,7 +82,7 @@ class BusBlocker(params: BusBlockerParams)(implicit p: Parameters) extends TLBus
 
   lazy val module = new LazyModuleImp(this) {
     // We need to be able to represent +1 larger than the largest populated address
-    val addressBits = log2Ceil(nodeOut.out(0)._2.manager.maxAddress+1+1)
+    val addressBits = log2Ceil(nodeOut.edges.out(0).manager.maxAddress+1+1)
     val pmps = RegInit(Vec.fill(params.pmpRegisters) { DevicePMP(addressBits, params.pageBits) })
     val blocks = pmps.tail.map(_.blockPriorAddress) :+ Bool(false)
     controlNode.regmap(0 -> (pmps zip blocks).map { case (p, b) => p.fields(b) }.toList.flatten)

src/main/scala/devices/tilelink/Clint.scala

@@ -68,7 +68,8 @@ class CoreplexLocalInterrupter(params: ClintParams)(implicit p: Parameters) exte
     val timecmp = Seq.fill(nTiles) { Seq.fill(timeWidth/regWidth)(Reg(UInt(width = regWidth))) }
     val ipi = Seq.fill(nTiles) { RegInit(UInt(0, width = 1)) }
 
-    intnode.in.map(_._1).zipWithIndex.foreach { case (int, i) =>
+    val (intnode_in, _) = intnode.in.unzip
+    intnode_in.zipWithIndex.foreach { case (int, i) =>
       int(0) := ShiftRegister(ipi(i)(0), params.intStages) // msip
       int(1) := ShiftRegister(time.asUInt >= timecmp(i).asUInt, params.intStages) // mtip
     }

src/main/scala/devices/tilelink/Plic.scala

@@ -91,12 +91,12 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
     sinkFn         = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) })
 
   /* Negotiated sizes */
-  def nDevices: Int = intnode.in.map(_._2.source.num).sum
+  def nDevices: Int = intnode.edges.in.map(_.source.num).sum
   def nPriorities = min(params.maxPriorities, nDevices)
-  def nHarts = intnode.out.map(_._2.source.num).sum
+  def nHarts = intnode.edges.out.map(_.source.num).sum
 
   // Assign all the devices unique ranges
-  lazy val sources = intnode.in.map(_._2.source)
+  lazy val sources = intnode.edges.in.map(_.source)
   lazy val flatSources = (sources zip sources.map(_.num).scanLeft(0)(_+_).init).map {
     case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o)))
   }.flatten