riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

WIP bugfixes: run until corrupted WB data (beats repeated)

Browse Source
This commit is contained in:
Henry Cook
2016-11-11 18:34:48 -08:00
parent 71315d5cf5
commit b7730d66f2
7 changed files with 70 additions and 51 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/rocket/tile.scala
View File

@ -27,7 +27,7 @@ class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
val dcacheParams = p.alterPartial({
case CacheName => "L1D"
case TLId => "L1toL2"
case TileId => tileId // TODO using this messes with Heirarchical P&R
case TileId => tileId // TODO using this messes with Heirarchical P&R: change to io.hartid?
})
val icacheParams = p.alterPartial({
case CacheName => "L1I"