riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

use address map instead of MMIOBase to find size of memory

Browse Source
This commit is contained in:
Howard Mao
2016-04-21 15:34:28 -07:00
committed by Andrew Waterman
parent 2d6f35525e
commit b7527268bb
4 changed files with 9 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
rocket/src/main/scala/rocket.scala
View File

@ -48,7 +48,6 @@ trait HasCoreParameters extends HasAddrMapParameters {
val vpnBitsExtended = vpnBits + (vaddrBits < xLen).toInt
val vaddrBitsExtended = vpnBitsExtended + pgIdxBits
val coreMaxAddrBits = paddrBits max vaddrBitsExtended
val mmioBase = p(MMIOBase)
val nCustomMrwCsrs = p(NCustomMRWCSRs)
val roccCsrs = if (p(BuildRoCC).isEmpty) Nil
else p(BuildRoCC).flatMap(_.csrs)