From b7527268bb23ef0852eb02b6b0c3a92416ac9e80 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Thu, 21 Apr 2016 15:34:28 -0700
Subject: [PATCH] use address map instead of MMIOBase to find size of memory

---
 rocket/src/main/scala/csr.scala      | 3 ++-
 rocket/src/main/scala/dma.scala      | 8 +++++---
 rocket/src/main/scala/nbdcache.scala | 4 ++--
 rocket/src/main/scala/rocket.scala   | 1 -
 4 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/rocket/src/main/scala/csr.scala b/rocket/src/main/scala/csr.scala
index 4186cf5e..606fb10a 100644
--- a/rocket/src/main/scala/csr.scala
+++ b/rocket/src/main/scala/csr.scala
@@ -8,6 +8,7 @@ import Instructions._
 import cde.{Parameters, Field}
 import uncore._
 import scala.math._
+import junctions.{AddrHashMap, GlobalAddrMap}
 
 class MStatus extends Bundle {
   val prv = UInt(width = PRV.SZ) // not truly part of mstatus, but convenient
@@ -227,7 +228,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
     CSRs.misa -> UInt(isa),
     CSRs.mstatus -> read_mstatus,
     CSRs.mtvec -> reg_mtvec,
-    CSRs.mcfgaddr -> UInt(p(junctions.MMIOBase)),
+    CSRs.mcfgaddr -> UInt(addrMap("mem").size),
     CSRs.mipi -> reg_mip.msip,
     CSRs.mip -> read_mip,
     CSRs.mie -> reg_mie,
diff --git a/rocket/src/main/scala/dma.scala b/rocket/src/main/scala/dma.scala
index a31e311e..a18d8644 100644
--- a/rocket/src/main/scala/dma.scala
+++ b/rocket/src/main/scala/dma.scala
@@ -3,7 +3,7 @@ package rocket
 import Chisel._
 import uncore._
 import uncore.DmaRequest._
-import junctions.ParameterizedBundle
+import junctions.{ParameterizedBundle, AddrHashMap, GlobalAddrMap}
 import cde.Parameters
 
 trait HasClientDmaParameters extends HasCoreParameters with HasDmaParameters {
@@ -165,8 +165,10 @@ class DmaFrontend(implicit p: Parameters) extends CoreModule()(p)
   }
 
   def check_region(cmd: UInt, src: UInt, dst: UInt): Bool = {
-    val dst_ok = Mux(cmd === DMA_CMD_SOUT, dst >= UInt(mmioBase), dst < UInt(mmioBase))
-    val src_ok = Mux(cmd === DMA_CMD_SIN,  src >= UInt(mmioBase), Bool(true))
+    val src_cacheable = addrMap.isCacheable(src)
+    val dst_cacheable = addrMap.isCacheable(dst)
+    val dst_ok = Mux(cmd === DMA_CMD_SOUT, !dst_cacheable, dst_cacheable)
+    val src_ok = Mux(cmd === DMA_CMD_SIN,  !src_cacheable, Bool(true))
     dst_ok && src_ok
   }
 
diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index 83d7b9da..ade7ed85 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -421,8 +421,8 @@ class MSHRFile(implicit p: Parameters) extends L1HellaCacheModule()(p) {
     val fence_rdy = Bool(OUTPUT)
   }
 
-  // determine if the request is in the memory region or mmio region
-  val cacheable = io.req.bits.addr < UInt(mmioBase)
+  // determine if the request is cacheable or not
+  val cacheable = addrMap.isCacheable(io.req.bits.addr)
 
   val sdq_val = Reg(init=Bits(0, sdqDepth))
   val sdq_alloc_id = PriorityEncoder(~sdq_val(sdqDepth-1,0))
diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala
index 81778134..b4b9601a 100644
--- a/rocket/src/main/scala/rocket.scala
+++ b/rocket/src/main/scala/rocket.scala
@@ -48,7 +48,6 @@ trait HasCoreParameters extends HasAddrMapParameters {
   val vpnBitsExtended = vpnBits + (vaddrBits < xLen).toInt
   val vaddrBitsExtended = vpnBitsExtended + pgIdxBits
   val coreMaxAddrBits = paddrBits max vaddrBitsExtended
-  val mmioBase = p(MMIOBase)
   val nCustomMrwCsrs = p(NCustomMRWCSRs)
   val roccCsrs = if (p(BuildRoCC).isEmpty) Nil
     else p(BuildRoCC).flatMap(_.csrs)