riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

use address map instead of MMIOBase to find size of memory

Browse Source
This commit is contained in:
Howard Mao
2016-04-21 15:34:28 -07:00
committed by Andrew Waterman
parent 2d6f35525e
commit b7527268bb
4 changed files with 9 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
rocket/src/main/scala/nbdcache.scala
View File

@ -421,8 +421,8 @@ class MSHRFile(implicit p: Parameters) extends L1HellaCacheModule()(p) {
val fence_rdy = Bool(OUTPUT)
}
// determine if the request is in the memory region or mmio region
val cacheable = io.req.bits.addr < UInt(mmioBase)
// determine if the request is cacheable or not
val cacheable = addrMap.isCacheable(io.req.bits.addr)
val sdq_val = Reg(init=Bits(0, sdqDepth))
val sdq_alloc_id = PriorityEncoder(~sdq_val(sdqDepth-1,0))